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* soc/amd/picasso: Generate GNB IO-APIC PCI routing tableRaul E Rangel2021-01-081-30/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for generating a PCI routing table that routes to the GNB IO-APIC. This means we no longer need to route to the FCH IO-APIC for PCI interrupts. BUG=b:170595019 TEST=Boot ezkinil to OS with `pci=nomsi amd_iommu=off` and verify all peripherals are working CPU0 CPU1 0: 112 0 IO-APIC 2-edge timer 1: 0 99 IO-APIC 1-edge i8042 4: 0 2523 IO-APIC 4-edge ttyS0 5: 34632 0 IO-APIC 5-fasteoi mmc1 7: 5646 0 IO-APIC 7-fasteoi pinctrl_amd 8: 0 0 IO-APIC 8-edge rtc0 9: 0 33 IO-APIC 9-fasteoi acpi 10: 88258 0 IO-APIC 10-edge AMD0010:00 11: 0 32485 IO-APIC 11-edge AMD0010:01 24: 3301 0 amd_gpio 3 cr50_i2c 25: 0 235214 IO-APIC 28-fasteoi amdgpu 26: 67408 0 IO-APIC 31-fasteoi xhci-hcd:usb1 27: 0 488876 IO-APIC 8-fasteoi mmc0 28: 1265 0 amd_gpio 9 PNP0C50:00 29: 656 0 amd_gpio 12 ELAN9004:00 30: 413 0 amd_gpio 31 chromeos-ec 31: 14153 0 IO-APIC 4-fasteoi ath10k_pci 32: 2 0 sysfstrig0 cros-ec-accel_consumer3 33: 2 0 sysfstrig0 cros-ec-accel_consumer0 34: 6 0 amd_gpio 62 rt5682 35: 0 38937 IO-APIC 29-fasteoi snd_hda_intel:card0, ACP3x_I2S_IRQ Cq-Depend: chrome-internal:3452710 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3211ab351a332fafb7b5f9ef486bb6646d9a214c Reviewed-on: https://review.coreboot.org/c/coreboot/+/48668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* cbfstool: Use flock() when accessing CBFS filesJulius Werner2021-01-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Trying to do multiple operations on the same CBFS image at the same time likely leads to data corruption. For this reason, add BSD advisory file locking (flock()) to cbfstool (and ifittool which is using the same file I/O library), so that only one process will operate on the same file at the same time and the others will wait in line. This should help resolve parallel build issues with the INTERMEDIATE target on certain platforms. Unfortunately, some platforms use the INTERMEDIATE target to do a direct dd into the CBFS image. This should generally be discouraged and future platforms should aim to clearly deliminate regions that need to be written directly by platform scripts with custom FMAP sections, so that they can be written with `cbfstool write`. For the time being, update the legacy platforms that do this with explicit calls to the `flock` utility. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I022468f6957415ae68a7a7e70428ae6f82d23b06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Furquan Shaikh <furquan@google.com>
* ACPI: Remove ACPI_NO_SMI_GNVSKyösti Mälkki2021-01-072-2/+0
| | | | | | | | | | | | | This was used as a guard to not raise SMI with APM_CNT_GNVS_UPDATE. The handler has been removed now completely. Change-Id: I7726367fd16630aa4b4b25b24b05f740645066db Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* soc/amd/picasso: Add GRXS and GTXS methodEric Lai2021-01-072-46/+51
| | | | | | | | | | | | | | | | Add GRXS and GTXS into gpiolib. We can align with Intel ACPI method for the better usage. This benefits acpi.c to be more clear, too. BUG=b:176270381 BRANCH=zork TEST=Confirm the Goodix touchscreen functional. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I1aa6a8f44f20577e679336889c849dd67cb99f2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/48944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/picasso: Add STXS and CTXS methodEric Lai2021-01-072-41/+46
| | | | | | | | | | | | | | | | Add STXS and CTXS into gpiolib. We can align with Intel ACPI method for the better usage. This benefits acpi.c to be more clear, too. BUG=b:176270381 BRANCH=zork TEST=Confirm the Goodix touchscreen functional. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: If4fcd68496a712fdccf44b91a6192ef58a0a9733 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48943 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86: Move prologue to .init sectionKyösti Mälkki2021-01-072-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | For arch/x86 the realmode part has to be located within the same 64 KiB as the reset vector. Some older intel platforms also require 4 KiB alignment for _start16bit. To enforce the above, and to separate required parts of .text without matching *(.text.*) rules in linker scripts, tag the pre-C environment assembly code with section .init directive. Description of .init section for ELF: This section holds executable instructions that contribute to the process initialization code. When a program starts to run, the system arranges to execute the code in this section before calling the main program entry point (called main for C programs). Change-Id: If32518b1c19d08935727330314904b52a246af3c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47599 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/picasso: Correctly populate the PCI interrupt line registerRaul E Rangel2021-01-063-0/+57
| | | | | | | | | | | | | | | | | | | The PCI interrupt line registers are used as a last resort if routing can't be fetched from either ACPI or the MPTable. This change correctly sets the registers. It overrides the pirq_data set by the mainboards since the routing is fixed in AGESA. BUG=b:170595019 TEST=Boot ezkinil with `pci=nomsi,noacpi amd_iommu=off noapic` Verified all PCI peripherals are still functional. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: If5d4d8f613c8d0fa9b43cefa804824681c3410d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/amd/picasso: Fix ACPI PCI routing tableRaul E Rangel2021-01-063-14/+158
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The original routing table did not handle all 8 INTx interrupts. Additionally it also didn't take the swizzling into account. Now that we know how AGESA programs the routing table we can correctly generate it. We still route the PCI interrupts through the FCH IOAPIC. A follow up will have the GNB IOAPIC handle the PCI interrupts. There is still work to be done to fix the legacy PCI_IRQ register for each PCI device. We can then remove the mainboard_pirq_data from each mainboard. BUG=b:170595019 TEST=Used ezkinil Boot kernel with `pci=nomsi amd_iommu=off noapic` and `pci=nomsi amd_iommu=off` then verified system was usable and verified /proc/interrupts looked correct. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I2b2cce9913081d5cd456043ba619a79c1dfd4a8e Reviewed-on: https://review.coreboot.org/c/coreboot/+/48632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/picasso/root_complex: add missing set_resourcesFelix Held2021-01-061-0/+1
| | | | | | | | | | | | The set_resources field in the root_complex_operations struct shouldn't be NULL, but a pointer to noop_set_resources instead. This fixes the error "PCI: 00:00.0 missing set_resources". Change-Id: I2d9f3850b3051c92cd9c0f52f8570f4fd6133070 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/amd/common/block/gpio_banks: fix sequence in gpio_outputFelix Held2021-01-061-1/+2
| | | | | | | | | | | | | When configuring a GPIO pin as output the value should be written before it gets configures as an output to avoid a possible glitch on the output when the GPIO pin was an input before and the output value was different from the one that got written afterwards. Change-Id: I2bb5e629ef0ed2daadc903ecc1852200fe3a5cb9 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/common/block/gpio_banks: clear output enable in gpio_input_*Felix Held2021-01-061-2/+2
| | | | | | | | | | | | | The functions to configure a GPIO as input with pull-up/down need to clear the output enable bit, so that the direction will be input. If the pin was configured as output before, the pin direction was still output after this call which is at least unexpected. Change-Id: Id1fa1669195080b34fd62324616825415728b0b4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/common/block/gpio_banks: clear pull-up/down bits in gpio_inputFelix Held2021-01-061-1/+1
| | | | | | | | | | | If the pin was configured as pull-up/down before this wouldn't get cleared when calling gpio_input before. Change-Id: I17d5eccb7492138e64abaecbd7cb853adb8c4d2d Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/picasso: Separate CPUID defs into new headerJason Glenesk2021-01-021-0/+1
| | | | | | | | | | | | | | Move CPUID definitions out of msr.h into new cpuid.h header. BUG=b:155307433 BRANCH=Zork Change-Id: I2ed5e0a5a6dbdb38fce8bf3e769f680330718653 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/common/psp: Remove files from bootblockMarshall Dawson2020-12-221-3/+0
| | | | | | | | | Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I8d775d2d813cf92245f3be4d41b3295ca6da18ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/48798 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/stoneyridge: Remove unused psp.hMarshall Dawson2020-12-221-1/+0
| | | | | | | | | | | psp.h was first included when Stoney Ridge began loading the first SMU firmware. That step was later moved from bootblock to romstage. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Id646390ce377143d09455f797de1b149dbb615b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48797 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/picasso: move sb_clk_output_48Mhz from acp to fchEric Lai2020-12-192-3/+2
| | | | | | | | | | | | | | | | Move sb_clk_output_48Mhz out of acp. It should be called unconditionally. We may have another device need this clock e.g. superio chip. BUG=b:174121847 BRANCH=zork TEST= build passed Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I30ad6c60066f17cc83e7feb40675610f4853a022 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/picasso: Add acp_i2s_use_external_48mhz_osc flagEric Lai2020-12-182-1/+9
| | | | | | | | | | | | | | | | If we have use external clock source for I2S, we don't need to enable internal one. Add acp_i2s_use_external_48mhz_osc flag for the project which uses external clock source. BUG=b:174121847 BRANCH=zork TEST= build passed Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ica68ee2da5a05231eb6db0218bd0f19907507273 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48637 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/cezanne: add GPIO supportFelix Held2020-12-183-0/+59
| | | | | | | | | | | | This still uses the common GPIO code that supports setting up SMI/SCI support for the GPIOs in all stages, which will get removed in future patches, so for now the SoC's gpio.c needs to be included in all stages. Change-Id: I6c12d1d6c605b7eb063eef62a1f71860f602f8dd Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48565 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/cezanne: Add SMI supportZheng Bao2020-12-183-0/+183
| | | | | | | | | Change-Id: I83b9a91cbab297d032292997a4d5768b89fe97dd Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48645 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/cezanne: add GPIO definitionsFelix Held2020-12-171-0/+285
| | | | | | | | Change-Id: I67930267a89ba0c64ec7e40e2bfa30a0618d104b Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/picasso: Fix the typo in GPIO defineZheng Bao2020-12-161-1/+1
| | | | | | | | | Change-Id: I8c9eed5d0e320b02382c24304a44e51e89eb6ac5 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/common/gpio_banks: Drop underscore in __gpioKyösti Mälkki2020-12-161-16/+16
| | | | | | | | | | | | The local function names were chosen such that they don't collide with <gpio.h> so the prefix is unnecessary. Change-Id: I4799a6d6b87e8081324d88b0773e61cbda0d4cfb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* arch/x86: Clean up bootblock assemblyKyösti Mälkki2020-12-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | We have identical gdtptr16 and gdtptr. The reference in gdtptr_offset calculation is not accounted for when considering --gc-sections, so to support linking gdt_init.S separately add dummy use of gdtptr symbol. Realmode execution already accessed gdt that was located outside [_start16bit,_estart16bit] region. Remove latter symbol as the former was not really a start of region, but entry point symbol. With the romcc bootblock solution, entry32.inc may have been linked into romstage before, but the !ENV_BOOTBLOCK case seems obsolete now. Change-Id: I0a3f6aeb217ca4e38b936b8c9ec8b0b69732cbb9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/amd/common: Use only byte access for IOMUXKyösti Mälkki2020-12-161-20/+2
| | | | | | | | | | Change-Id: Ia3c4fb41b5851b1c0ffc6bbec7d1c051e232fc94 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42978 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/picasso/smi: add missing bits to GEVENT_MASKFelix Held2020-12-151-1/+3
| | | | | | | | | | | GEVENT_MASK should cover all GEVENT pins, but was missing SMITYPE_G_AGPIO9 and SMITYPE_G_AGPIO8. Change-Id: Ia676476e2d2cf468d82d6d90e9fc11d34f56f153 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/common,picasso: Place some ENV_X86 guardsKyösti Mälkki2020-12-152-6/+20
| | | | | | | | | | | | | | | Base address symbols for ACPIMMIO banks that would not get assigned at runtime must not resolve at linker-stage either. The build of PSP-verstage should pass without the preprocessor macros that have x86-centric view of memory space. Change-Id: I3cb1b5a90023ebc4359835be716c5e3f9451df60 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/amd/common: Move lpc_util to verstage_x86Kyösti Mälkki2020-12-151-1/+1
| | | | | | | | | | The file seems to be all about PCI configuration access. Change-Id: I1e64d3d7df3caa33ee92961fe7246d03f2707ab4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43328 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common: Redo ACPIMMIO_BASE and _BANKKyösti Mälkki2020-12-153-11/+5
| | | | | | | | | | Change-Id: I31f2d04d9fc8bdd9e270fb3cb48d71f215999a50 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42894 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common: Refactor SMBus base argumentsKyösti Mälkki2020-12-154-34/+20
| | | | | | | | | | | Replace SMBus base addresses with proper symbols. Change-Id: I5e0ebd7609c5c83d0e443ffba74dae68017d3ebc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42074 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/*/include/spc/gpio: fix pin numbers in commentsFelix Held2020-12-132-4/+4
| | | | | | | | Change-Id: I9e91f28659c49927aaa4c7cd67f73bb11258c27c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48563 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/common/block/gpio: use all-y in MakefileFelix Held2020-12-131-5/+1
| | | | | | | | Change-Id: Ib77e3d088cc07da4e43a63afb863bb90796f9a37 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/cezanne: add caching setup in bootblockFelix Held2020-12-133-0/+84
| | | | | | | | | | | | The code can likely be factored out to common code, but since I'm not entirely sure yet that there will be no differences, I'll copy for now instead. Change-Id: I5fc158518cf9534ab9727f3305abeb4b34049e76 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48517 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/common: Remove SMBus host word accessorsKyösti Mälkki2020-12-121-20/+0
| | | | | | | | | | | | SMBus controller has byte-wide registers. Remove the word accessors. Change-Id: If396108308bc8303d84458039b9529ecd83276c9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/common: Refactor ACPIMMIO posted writesKyösti Mälkki2020-12-123-8/+6
| | | | | | | | | | Change-Id: Ic1a5c17c789dd79fea8f348d1a9d32d4301ced88 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42825 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Revert "src/amd/common: Exclude biosram from psp_verstage"Kyösti Mälkki2020-12-121-5/+1
| | | | | | | | | | | | | | | This reverts commit f38af663d2c2c854859715803da249e6c24032db. The build error was a spurious ENV_X86 guard in <cbmem.h> that called for a different clean up. Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Change-Id: I0a995301404b67224be6addbeebf984c4b5c47d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43067 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* amdfwtool: Register APCB and APCB_BK respectivelyZheng Bao2020-12-111-1/+5
| | | | | | | | | | | We took the assumption the APCB(0x60) and APCB_BK(0x68) are the same file. For picasso, they are. For later programe, they are not. Change-Id: Idea7847691c2b511b489c306f04a8cb8945fd057 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/picasso: Add data fabric read helper functionJason Glenesk2020-12-112-0/+36
| | | | | | | | | | | | | | | | Add new helper function to support reading a register from the data fabric. BUG=b:155307433 TEST=Boot trembyle with If64fd624597b2ced014ba7f0332a6a48143c0e8c and confirm read values match expected values. BRANCH=Zork Change-Id: If0dc72063fbb99efaeea3fccef16cc1b5b8526f1 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47726 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/cezanne: add 0xcf9 resetFelix Held2020-12-116-1/+67
| | | | | | | | | Change-Id: Ibb78661c102e0d0327f3e74173bf98bc40e13960 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48488 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/picasso: move chipset_handle_reset to commonFelix Held2020-12-114-11/+20
| | | | | | | | | | | | The FSP integration code needs this function to be present. It's not supposed to be called, but if it is, it'll print an error and call the SoC's cold reset function. Change-Id: I15f2622d9d9d0f22e3cf8e6283b578f5933b1a9f Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/picasso: factor out write_resume_eip to common codeFelix Held2020-12-114-21/+37
| | | | | | | | Change-Id: I24454aa9e2ccc98b2aceb6b189e072e6e50b8b30 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/picasso: move UART console code to common folderFelix Held2020-12-113-5/+15
| | | | | | | | Change-Id: Ibc9a4c05bdfc7cd3cd0eada67563386c95d2b50e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/picasso: move UART Kconfig options to common folderFelix Held2020-12-112-47/+58
| | | | | | | | | | | The actual UART initialization code will be factored out in follow-up commits. Change-Id: Ie4ddf1951b230323c5480c4389376c62dd74b0e1 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/picasso: rename PICASSO_CONSOLE_UART to AMD_SOC_CONSOLE_UARTFelix Held2020-12-116-19/+19
| | | | | | | | | | | | This allows factoring out the common initialization for the integrated UARTs. Change-Id: I7399a13b9280b732086c6f8e6dfd9f1207d8c8ff Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48508 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/piasso,cezanne: add warning about using all-y in Makefile.incFelix Held2020-12-112-0/+2
| | | | | | | | | | | | | all-y will also add a compilation unit to the verstage on PSP build that runs on an ARM code instead of a x86 one. At the moment Cezanne doesn't have verstage on PSP support yet, but since it'll eventually land it doesn't hurt to already add the comment now. Change-Id: I15fb66e796cab48737ba5ac463c4c973794a005a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/picasso: use all-y for aoac targetFelix Held2020-12-111-4/+1
| | | | | | | | | | | Since aoac gets also linked into verstage on PSP, all-y can be used here. Change-Id: I74607123ebc8115aa7efbb9a364d9632372b52cb Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48506 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/picasso/aoac: only check FCH_AOAC_UART_FOR_CONSOLE if usedFelix Held2020-12-111-1/+1
| | | | | | | | | | | | FCH_AOAC_UART_FOR_CONSOLE will only be used in the code if PICASSO_CONSOLE_UART is selected, so only check if it's a valid value in this case. Change-Id: I103dd8d469a084c7dc7dcf55175b1f77f900adc5 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48485 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/stoneyridge/reset: use port and bit defines from cf9_reset.hFelix Held2020-12-103-8/+3
| | | | | | | | | | | | The register name and the name of one bit are slightly different, but have the same functionality. Change-Id: Ie49975bb43868cbb2dc986e66dc5b7291e70222f Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48507 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/picasso/reset: use port and bit defines from cf9_reset.hFelix Held2020-12-103-8/+3
| | | | | | | | | | | | The register name and the name of one bit are slightly different, but have the same functionality. Change-Id: I025f1c7b2c7643afe245f2275ae6ef45e64b951a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48487 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/picasso/reset: remove leftover PCI includesFelix Held2020-12-101-2/+0
| | | | | | | | | | | | On Stoneyridge some PCI registers were accessed in this compilation unit, but on Picasso this is no longer the case. Change-Id: Ifbf65f9724a14d4847af98930759c865453775b4 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48486 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/cezanne: print APU family and model in bootblock_soc_initFelix Held2020-12-091-0/+3
| | | | | | | | Change-Id: I457188c905167affc1ebcea835a36df822ecb23c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-11 01:48:12 +0000