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path: root/src/soc/imgtec
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* linking: link bootblock.elf with .data and .bss sections againAaron Durbin2015-09-221-7/+1
* verstage: use common program.ld for linkingAaron Durbin2015-09-091-1/+0
* imgtec/pistachio: remove timestamp_get() implementationAaron Durbin2015-08-311-6/+1
* imgtech/pistacho: Add vboot2 memory regionPatrick Georgi2015-08-091-1/+3
* Remove address from GPLv2 headersPatrick Georgi2015-06-241-2/+1
* Remove old HAVE_UART_MEMORY_MAPPED select statementsMartin Roth2015-06-211-1/+0
* pistachio: add DDR3 initialization codeIonela Voinescu2015-06-125-112/+655
* pistachio: Use passive windowing as DQS gating schemeIonela Voinescu2015-06-121-0/+23
* pistachio: sort included header filesIonela Voinescu2015-06-107-13/+13
* pistachio: initialize cbmem area to be emptyIonela Voinescu2015-06-101-0/+7
* pistachio: increase romstage sizeIonela Voinescu2015-06-091-2/+2
* Revert "pistashio: bump up romstage size"Aaron Durbin2015-06-021-2/+2
* pistashio: bump up romstage sizeAaron Durbin2015-05-261-2/+2
* Remove address from GPLv2 headersPatrick Georgi2015-05-2112-20/+12
* Remove Kconfig variable that has no effectPatrick Georgi2015-05-191-1/+0
* imgtec/pistachio: Add comment on the unusual memory layoutPatrick Georgi2015-05-071-1/+4
* imgtech/pistachio: Give some more space to the bootblockPatrick Georgi2015-04-301-3/+3
* kbuild: automatically include SOCsStefan Reinauer2015-04-292-1/+3
* imgtec/pistachio: DDR reads return to controller with no bubblesIonela Voinescu2015-04-221-2/+2
* imgtec/pistachio: DDR row/bank/column mappingIonela Voinescu2015-04-221-2/+2
* soc: select generic gpio lib on (almost) all non-x86 SOCsStefan Reinauer2015-04-221-0/+1
* imgtec/pistachio: increase RAM CBFS cache sizeVadim Bendebury2015-04-221-2/+2
* pistachio: Remove 50% DDR bandwidth restrictionIonela Voinescu2015-04-211-1/+1
* pistachio: Decrease DDR ODT from 75R to 50RIonela Voinescu2015-04-211-1/+1
* pistachio: clean DDR2 initialization codeIonela Voinescu2015-04-211-155/+15
* pistachio: add clock setup for all I2C interfacesIonela Voinescu2015-04-212-19/+19
* urara: Identity map DRAM/SRAMAndrew Bresticker2015-04-212-11/+49
* imgtec/pistachio: Add spi_crop_chunk()Patrick Georgi2015-04-211-0/+5
* pistachio: Move console UART to a Kconfig variableDavid Hendricks2015-04-171-28/+5
* pistachio: add DDR2 initialization codeIonela Voinescu2015-04-174-1/+704
* pistachio: report UART register widthVadim Bendebury2015-04-171-1/+1
* uart: pass register width in the coreboot tableVadim Bendebury2015-04-171-0/+1
* pistachio: implement clock setup for I2C0Ionela Voinescu2015-04-142-0/+33
* pistachio: Fix ROM clock base addressIonela Voinescu2015-04-141-1/+1
* urara: add clock setup for MIPS CPU, ROM and EthernetIonela Voinescu2015-04-142-3/+80
* pistachio: fix clocks setup codeIonela Voinescu2015-04-141-6/+16
* pistachio: Use 1.8433179 MHz for UART refclkDavid Hendricks2015-04-141-2/+2
* pistachio: increase size of bootblock to 18 KBIonela Voinescu2015-04-141-3/+3
* pistachio: change memory layout as to allow bigger CBFS cacheIonela Voinescu2015-04-141-4/+5
* pistachio: spi: use same clock edge for RX and TXIonela Voinescu2015-04-141-0/+1
* urara: Configure clocks and MFIOsIonela Voinescu2015-04-143-0/+384
* CBFS: Automate ROM image layout and remove hardcoded offsetsJulius Werner2015-04-141-9/+0
* spi: support controllers with limited transfer size capabilitiesVadim Bendebury2015-04-131-0/+5
* urara: add support for DMA coherent memory areaIonela Voinescu2015-04-131-0/+2
* pistachio: increase the size of romstage to 36KIonela Voinescu2015-04-131-1/+1
* pistachio: add timer frequency for SOC; correct platform IDIonela Voinescu2015-04-092-7/+24
* pistachio: add SOC descriptorVadim Bendebury2015-04-092-0/+49
* pistachio: modify memory layoutVadim Bendebury2015-04-091-9/+10
* pistachio: set correct CBMEM top addressVadim Bendebury2015-04-091-2/+1
* pistachio: allow more room for bootblockVadim Bendebury2015-04-091-2/+2
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