| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | soc/intel/alderlake: Refactor PCIE port config | Eric Lai | 2021-02-05 | 1 | -21/+61 |
| * | soc/intel/alderlake: Disable Internal Gfx based on SOC_INTEL_DISABLE_IGD | Subrata Banik | 2021-01-21 | 1 | -5/+6 |
| * | soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs | Subrata Banik | 2021-01-10 | 1 | -5/+8 |
| * | src/soc/intel/alderlake: Enable the PCH HDA | V Sowmya | 2020-12-04 | 1 | -0/+3 |
| * | soc/intel/alderlake/romstage: Skip GPIO configuration from FSP | Subrata Banik | 2020-10-25 | 1 | -0/+3 |
| * | soc/intel/alderlake: Enable TME for Alder Lake | Subrata Banik | 2020-10-14 | 1 | -0/+2 |
| * | soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage | Subrata Banik | 2020-10-03 | 1 | -2/+2 |
| * | soc/intel/alderlake/romstage: Fix compilation issue | Subrata Banik | 2020-09-24 | 1 | -1/+1 |
| * | soc/intel/alderlake/romstage: Do initial SoC commit till romstage | Subrata Banik | 2020-09-15 | 1 | -0/+174 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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