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path: root/src/soc/intel/broadwell/Kconfig
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* soc/intel/broadwell: Drop old forked version of SMBUS supportKyösti Mälkki2020-01-091-0/+1
* arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHEKyösti Mälkki2019-12-191-10/+0
* sb/intel/common/spi: Add Baytrail/Braswell supportArthur Heymans2019-11-261-1/+1
* Kconfig: Drop the C_ENVIRONMENT_BOOTBLOCK symbolArthur Heymans2019-11-251-1/+0
* soc/intel/broadwell: Use common INTEL_SB SPI codeArthur Heymans2019-11-101-0/+1
* soc/intel/broadwell: Use common SB RTC codeArthur Heymans2019-11-101-0/+1
* intel/broadwell: Switch to TSC_MONOTONIC_TIMERKyösti Mälkki2019-11-031-0/+1
* cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATEKyösti Mälkki2019-11-031-1/+0
* arch/x86: Flip option NO_CAR_GLOBAL_MIGRATIONKyösti Mälkki2019-08-111-1/+0
* arch/x86: Enable POSTCAR_CONSOLE by defaultKyösti Mälkki2019-08-111-1/+0
* lib/stage_cache: Refactor Kconfig optionsKyösti Mälkki2019-08-081-1/+0
* arch/x86: Flip HAVE_MONOTONIC_TIMER defaultKyösti Mälkki2019-07-091-1/+0
* cpu/x86: Flip SMM_TSEG defaultKyösti Mälkki2019-07-091-1/+0
* {soc,northbridge}/Kconfig: Remove unused CACHE_MRC_SIZE_KBElyes HAOUAS2019-06-281-4/+0
* soc/intel/broadwell: Enable LPC/SIO setup in bootblockArthur Heymans2019-05-151-1/+0
* nb/intel/broadwell: Add an option for where verstage startsArthur Heymans2019-05-151-1/+24
* soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCKArthur Heymans2019-05-151-12/+9
* vboot: refactor OPROM codeJoel Kitching2019-04-301-1/+1
* cpu/intel/car/non-evict: Select NO_FIXED_XIP_ROM_SIZEArthur Heymans2019-04-251-0/+1
* vboot: Select CONFIG_VBOOT_OPROM_MATTERS in more casesJulius Werner2019-04-011-0/+1
* Kconfig: Unify power-after-failure optionsNico Huber2019-01-061-0/+2
* arch/x86: Use a common timestamp.inc with romcc bootblocksKyösti Mälkki2018-12-301-4/+0
* soc/intel/*: Select SUPPORT_CPU_UCODE_IN_CBFS only onceArthur Heymans2018-12-241-1/+0
* soc/intel/broadwell: Implement postcar stageArthur Heymans2018-12-051-0/+2
* soc/intel/{broadwell,skylake}: Remove unused SERIAL_CPU_INITElyes HAOUAS2018-11-161-4/+0
* intel: Use CF9 reset (part 1)Patrick Rudolph2018-10-221-1/+1
* src/*/intel/: clarify Kconfig options regarding IFDStefan Tauner2018-09-131-1/+1
* soc/intel/broadwell/Kconfig: Clean up redefined config optionsArthur Heymans2018-08-131-6/+0
* arch/x86: Make RELOCATABLE_RAMSTAGE the defaultKyösti Mälkki2018-06-061-4/+1
* intel/broadwell: Add option to enable/disable the PCIe AER capabilityYouness Alaoui2018-05-081-0/+4
* soc/intel/broadwell: add support for Intel GMA OpRegionMatt DeVillier2018-03-151-0/+1
* soc/intel/broadwell: remove CACHE_MRC_SETTINGS optionAaron Durbin2017-12-171-4/+0
* usbdebug: Remove redundant setupKyösti Mälkki2017-08-071-4/+0
* soc/broadwell: Allow disabling of PCIe ASPM optionsYouness Alaoui2017-06-091-4/+16
* vboot: Select SoC-specific configuration for all Chrome OS boardsJulius Werner2017-03-281-0/+3
* Revert "intel/lynxpoint,broadwell: Fix eDP display in Windows, SeaBios & Tiano"Matt DeVillier2017-02-201-9/+0
* cpu/intel/common: Add/Use common function to set virtualizationMatt DeVillier2016-12-271-1/+1
* MMCONF_SUPPORT: Flip default to enabledKyösti Mälkki2016-12-071-1/+0
* Remove explicit select MMCONF_SUPPORTKyösti Mälkki2016-11-221-1/+0
* intel car: Remove references to DCACHE_RAM_ROMSTACK_SIZEKyösti Mälkki2016-11-081-7/+0
* Kconfig: Update default hex values to start with 0xMartin Roth2016-10-021-1/+1
* Kconfig: introduce writable boot device notionAaron Durbin2016-08-191-0/+1
* chromeos chipsets: select RTC usageAaron Durbin2016-08-081-0/+1
* intel/lynxpoint,broadwell: Fix eDP display in Windows, SeaBios & TianoPrabal Saha2016-08-021-0/+9
* src/soc: Capitalize CPU, ACPI, RAM and ROMElyes HAOUAS2016-07-311-1/+1
* soc/intel/broadwell: use common Intel ACPI hardware definitionsAaron Durbin2016-07-151-0/+1
* cpu/x86: remove BACKUP_DEFAULT_SMM_REGION optionAaron Durbin2016-05-041-1/+0
* Add EM100 'hyper term' spi console support in ramstage & smmMartin Roth2015-10-051-0/+1
* broadwell: Switch to using common ACPI _SWS codeDuncan Laurie2015-09-171-0/+1
* Move final Intel chipsets with ME to intel/common/firmwareMartin Roth2015-09-161-66/+3
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