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coreboot.git
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4.1
4.10_branch
4.11_branch
4.12_branch
4.14_branch
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4.18_branch
4.19_branch
4.2
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4.22_branch
4.3
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Coreboot firmware sources
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path:
root
/
src
/
soc
/
intel
/
cannonlake
/
acpi
/
southbridge.asl
Commit message (
Expand
)
Author
Age
Files
Lines
*
soc: Remove copyright notices
Patrick Georgi
2020-03-18
1
-2
/
+0
*
soc/intel/cannonlake: Add gfx.asl file
Mathew King
2019-12-02
1
-0
/
+3
*
soc/intel/{apl,cnl,dnv,icl,skl}: Move lpc.asl into common/block/acpi
Subrata Banik
2019-11-01
1
-1
/
+1
*
soc/intel/cannonlake: Remove unused header files from southbridge.asl
Aamir Bohra
2019-07-13
1
-5
/
+0
*
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
Julius Werner
2019-03-08
1
-1
/
+1
*
soc/intel/cnl/acpi: add ish ACPI device
Jett Rink
2019-03-04
1
-0
/
+3
*
soc/intel/cannonlake: Make static IRQ mapping for CNP PCH pci devices
Subrata Banik
2018-11-15
1
-3
/
+0
*
mb/{intel/google}: Move CNVi ASL entry from static DSDT to dynamic SSDT gener...
Subrata Banik
2018-11-07
1
-3
/
+0
*
soc/intel/cannonlake: Add CNP PCH-H gpio pin definitions
praveen hodagatta pranesh
2018-10-17
1
-0
/
+4
*
soc/intel/cannonlake: Add PCIE ASL entry
Subrata Banik
2018-10-09
1
-0
/
+3
*
soc/intel/cannonlake: Make correct IRQ mapping for CNL SA and PCH PCI devices
Subrata Banik
2018-10-09
1
-0
/
+7
*
soc/intel/cannonlake: Add ACPI entry for LAN
Lijian Zhao
2018-09-28
1
-1
/
+4
*
soc/intel/cannonlake: Fix comment errors for SMBUS
Lijian Zhao
2018-08-30
1
-1
/
+1
*
soc/intel/cannonlake: Clear EMMC timeout register
Lijian Zhao
2018-02-22
1
-3
/
+3
*
soc/intel/cannonlake: Use common PCR ASL
Lijian Zhao
2018-02-16
1
-1
/
+1
*
src/soc/intel/cannonlake: Add _PRW for CNVi
Bora Guvendik
2017-12-13
1
-0
/
+3
*
soc/intel/cannonlake: Add all the SOC level DSDT tables
Lijian Zhao
2017-10-05
1
-0
/
+18
*
soc/intel/cannonlake: add initial ASL methods for SCS, GPIO
Bora Guvendik
2017-10-03
1
-0
/
+9
*
soc/intel/cannonlake: Add PCIE IRQs
Bora Guvendik
2017-09-19
1
-0
/
+20