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* soc/intel/cannonlake: Clear EMMC timeout when boot source is not EMMCBora Guvendik2018-04-051-4/+24
* soc/intel/cannonlake: Clear EMMC timeout registerLijian Zhao2018-02-222-3/+13
* soc/intel/cannonlake: Update GPIO ASLLijian Zhao2018-02-161-5/+32
* soc/intel/cannonlake: Use common PCR ASLLijian Zhao2018-02-162-24/+1
* soc/intel/cannonlake: Add child CARD device into eMMC/SD controllerSubrata Banik2018-01-241-0/+20
* soc/intel/cannonlake: Port SD Controller W/A from Intel Reference codeSubrata Banik2018-01-241-2/+13
* soc/intel/cannonlake: Port eMMC controller W/A from Intel Reference codeSubrata Banik2018-01-241-4/+16
* src/soc/intel/cannonlake: Add _PRW for CNViBora Guvendik2017-12-132-0/+35
* soc/intel/cannonlake: Add PM methods to power gate SD card controllerVaibhav Shankar2017-11-231-0/+17
* soc/intel/cannonlake: Add ACPI workaround for EMMCLijian Zhao2017-11-201-0/+20
* soc/intel/cannonlake: Add cpu.asl fileShaunak Saha2017-11-171-0/+43
* soc/intel/cannonlake: Fix and clean up xhci ACPI codeVaibhav Shankar2017-11-151-142/+0
* soc/intel/cannonlake: Add platform.aslLijian Zhao2017-10-201-24/+2
* soc/intel/cannonlake: add length information for communitiesBora Guvendik2017-10-121-0/+6
* soc/intel/cannonlake: Add ACPI platform sleep capabilityVaibhav Shankar2017-10-121-0/+20
* soc/intel/cannonlake: Add all the SOC level DSDT tablesLijian Zhao2017-10-058-0/+635
* soc/intel/cannonlake: add initial ASL methods for SCS, GPIOBora Guvendik2017-10-034-0/+158
* soc/intel/cannonlake: Add northbridge dsdt tableLijian Zhao2017-10-031-5/+324
* soc/intel/cannonlake: Add PCIE IRQsBora Guvendik2017-09-193-0/+141
* soc/intel/cannonlake: Add common ACPI support for CNLLijian Zhao2017-09-131-0/+57
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