summaryrefslogtreecommitdiffstats
path: root/src/soc/intel/cannonlake/acpi
Commit message (Expand)AuthorAgeFilesLines
* soc/intel/cannonlake/acpi: Add board level s0ix call backEric Lai2019-05-061-0/+10
* coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner2019-03-082-3/+3
* soc/intel/cnl/acpi: add ish ACPI deviceJett Rink2019-03-042-0/+25
* soc/intel/cannonlake: Fix DSDT compile remarksLijian Zhao2019-03-042-6/+3
* soc/intel/cannonlake: Add a config for configuring SD_VDD1_PWR_EN#Rizwan Qureshi2019-02-271-0/+16
* soc/intel/cannonlake: Add ASL functions to manipulate RX/TX buffersRizwan Qureshi2019-02-271-0/+44
* soc/intel/cannonlake: Update GPIO definitions for Virtual GPIORizwan Qureshi2019-02-261-3/+3
* soc/intel/cannonlake: Add ASL function for setting pad modeRizwan Qureshi2019-02-221-0/+22
* src/soc/intel/cannonlake: Add _DSM methods for LPIT tableLijian Zhao2019-02-201-0/+76
* soc/intel/cannonlake: Replace device name B0D4 with TCPUSumeet Pawnikar2019-01-231-1/+1
* soc/intel/cannonlake: Add cannonlake ACPI GPIO opLijian Zhao2019-01-033-35/+77
* soc/intel/cannonlake: Fix GPIO reportingDuncan Laurie2018-12-102-23/+10
* soc/intel/cannonlake: Add DPTF ACPI codeDuncan Laurie2018-12-041-0/+45
* cpu/intel/common: Use a common acpi/cpu.asl fileArthur Heymans2018-11-301-35/+0
* soc/intel/common: Rework acpi/cpu.aslArthur Heymans2018-11-301-24/+16
* soc/intel/cannonlake: Make static IRQ mapping for CNP PCH pci devicesSubrata Banik2018-11-154-332/+51
* mb/{intel/google}: Move CNVi ASL entry from static DSDT to dynamic SSDT gener...Subrata Banik2018-11-072-35/+0
* soc/intel/cannonlake: Enable S4 sleep state supportpraveen hodagatta pranesh2018-10-251-1/+2
* soc/intel/cannonlake: Add CNP PCH-H gpio pin definitionspraveen hodagatta pranesh2018-10-172-0/+132
* soc/intel/cannonlake: Add PCIE ASL entrySubrata Banik2018-10-092-0/+385
* soc/intel/cannonlake: Make correct IRQ mapping for CNL SA and PCH PCI devicesSubrata Banik2018-10-093-80/+411
* soc/intel/cannonlake: Add ACPI entry for LANLijian Zhao2018-09-282-1/+33
* soc/intel/cannonlake: Fix comment errors for SMBUSLijian Zhao2018-08-301-1/+1
* soc/intel/cannonlake: Clear EMMC timeout when boot source is not EMMCBora Guvendik2018-04-051-4/+24
* soc/intel/cannonlake: Clear EMMC timeout registerLijian Zhao2018-02-222-3/+13
* soc/intel/cannonlake: Update GPIO ASLLijian Zhao2018-02-161-5/+32
* soc/intel/cannonlake: Use common PCR ASLLijian Zhao2018-02-162-24/+1
* soc/intel/cannonlake: Add child CARD device into eMMC/SD controllerSubrata Banik2018-01-241-0/+20
* soc/intel/cannonlake: Port SD Controller W/A from Intel Reference codeSubrata Banik2018-01-241-2/+13
* soc/intel/cannonlake: Port eMMC controller W/A from Intel Reference codeSubrata Banik2018-01-241-4/+16
* src/soc/intel/cannonlake: Add _PRW for CNViBora Guvendik2017-12-132-0/+35
* soc/intel/cannonlake: Add PM methods to power gate SD card controllerVaibhav Shankar2017-11-231-0/+17
* soc/intel/cannonlake: Add ACPI workaround for EMMCLijian Zhao2017-11-201-0/+20
* soc/intel/cannonlake: Add cpu.asl fileShaunak Saha2017-11-171-0/+43
* soc/intel/cannonlake: Fix and clean up xhci ACPI codeVaibhav Shankar2017-11-151-142/+0
* soc/intel/cannonlake: Add platform.aslLijian Zhao2017-10-201-24/+2
* soc/intel/cannonlake: add length information for communitiesBora Guvendik2017-10-121-0/+6
* soc/intel/cannonlake: Add ACPI platform sleep capabilityVaibhav Shankar2017-10-121-0/+20
* soc/intel/cannonlake: Add all the SOC level DSDT tablesLijian Zhao2017-10-058-0/+635
* soc/intel/cannonlake: add initial ASL methods for SCS, GPIOBora Guvendik2017-10-034-0/+158
* soc/intel/cannonlake: Add northbridge dsdt tableLijian Zhao2017-10-031-5/+324
* soc/intel/cannonlake: Add PCIE IRQsBora Guvendik2017-09-193-0/+141
* soc/intel/cannonlake: Add common ACPI support for CNLLijian Zhao2017-09-131-0/+57
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-16 18:06:14 +0000