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path: root/src/soc/intel/cannonlake/bootblock
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* soc/intel/cannonlake: Add report for iGD 0x3ea1Lijian Zhao2019-04-191-1/+2
* coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner2019-03-083-5/+5
* device/mmio.h: Add include file for MMIO opsKyösti Mälkki2019-03-041-0/+1
* arch/io.h: Drop unnecessary includeKyösti Mälkki2019-03-041-1/+0
* device/pci: Fix PCI accessor headersKyösti Mälkki2019-03-012-0/+2
* soc/intel/cannonlake: Add Comet Lake U SA 2+2 Device IDSubrata Banik2019-02-281-0/+1
* soc/intel/common: Include cometlake PCH IDsRonak Kanabar2019-02-261-0/+5
* soc/intel/common: Include cometlake SA IDsRonak Kanabar2019-02-241-0/+25
* soc/intel/common: Include cometlake CPU IDsRonak Kanabar2019-02-241-0/+4
* soc/intel/cannonlake: Make few more whitespace proper in MCH nameSubrata Banik2019-02-231-1/+1
* soc/intel/cannonlake: Add whitespace proper in CPU/MCH/IGD nameSubrata Banik2019-02-221-6/+6
* soc/intel/common: Add whiskeylake celeron v-0 supportLijian Zhao2019-02-191-0/+1
* soc/intel/common/block: Move tco common functions into block/smbusSubrata Banik2019-01-101-33/+3
* soc/intel: Clean mess around UART_DEBUGNico Huber2019-01-091-1/+1
* soc: Remove useless include <device/pci_ids.h>Elyes HAOUAS2018-12-191-1/+0
* cpuid: Add helper function for cpuid(1) functionsSubrata Banik2018-12-131-7/+8
* soc/intel/cannonlake: Load FSP teardown optionallyLijian Zhao2018-12-031-0/+3
* soc/intel/cannonlake: Fix IO decode setupDuncan Laurie2018-11-211-11/+29
* soc/intel: Consolidate FSP CAR setup and teardown codePraveen hodagatta pranesh2018-10-251-1/+19
* soc/intel/cannonlake: Add new cannon lake PCH-H supportpraveen hodagatta pranesh2018-10-171-0/+7
* soc/intel/cannonlake: Update PMC base address for CNP H and LPMaulik V Vaghela2018-08-301-8/+34
* soc/intel/common/block: Move common uart function to block/uartSubrata Banik2018-08-202-2/+4
* soc/intel/common/block: Add WHL 2-core SKUKrzysztof Sywula2018-08-201-1/+2
* src/soc/intel: Add new device IDs to support coffeelakeMaulik2018-08-101-3/+6
* soc/intel/cannonlake: Report Whiskey Lake infoLijian Zhao2018-08-031-0/+3
* src/soc: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS2018-07-091-1/+1
* soc/intel/common/block: Move p2sb common functions into block/p2sbSubrata Banik2018-06-281-21/+4
* src: Use of device_t is deprecatedElyes HAOUAS2018-06-142-6/+6
* bootblock: Allow more timestamps in bootblock_main_with_timestamp()Julius Werner2018-05-221-1/+1
* soc/intel/cannonlake: Add Cannonlake D0 support in mpinit and reportLijian Zhao2018-01-261-0/+1
* soc/intel/cannonlake: enable pch link in bootblockCaveh Jalali2018-01-251-0/+4
* soc/intel/cannonlake: Program DMI PCR settingsLijian Zhao2018-01-161-6/+1
* soc/intel/cannonlake: Add a call to gspi_early_bar_init in bootblockFurquan Shaikh2018-01-101-0/+2
* soc/intel/cannonlake: Remove redundent CNL CPUID macrosSubrata Banik2018-01-091-2/+2
* soc/intel/cannonlake: Correct PMC/GPIO routing informationLijian Zhao2018-01-051-0/+4
* soc/intel/cannonlake: Add PCH ID support in bootblock/report_platform.cSubrata Banik2017-12-081-5/+44
* soc/intel/cannonlake: Fix HECI error on resetLijian Zhao2017-10-191-3/+0
* soc/intel/cannonlake: Use EBDA area to store cbmem_top addressSubrata Banik2017-10-181-2/+0
* soc/intel/cannonlake: Enable common PMC code for CNLLijian Zhao2017-08-211-1/+1
* soc/intel/cannonlake: Add memory map supportLijian Zhao2017-08-071-0/+2
* Fix files with multiple newlines at the end.Martin Roth2017-07-241-1/+0
* soc/intel/cannonlake: Keep variable from going out of scopeMartin Roth2017-07-221-1/+1
* soc/intel/cannonlake: Fix Build breakLijian Zhao2017-07-182-2/+1
* soc/intel/cannonlake: Add bootblock PCHAndrey Petrov2017-07-131-0/+199
* soc/intel/cannonlake: Add early CPU initializationAndrey Petrov2017-07-131-0/+28
* soc/intel/cannonlake: Add report_platform.cAndrey Petrov2017-07-121-0/+159
* soc/intel/cannonlake: Add bootblock.cAndrey Petrov2017-07-021-0/+43
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