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path: root/src/soc/intel/cannonlake/fsp_params.c
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* soc/intel: transition full control over PM Timer from FSP to corebootMichael Niewöhner2021-10-171-1/+8
* soc/intel/cannonlake: Lock PAM registers in finalizeTim Wawrzynczak2021-09-051-0/+1
* soc/intel/cannonlake: Fix PCH-H IRQ constraintsAngel Pons2021-08-251-0/+6
* soc/intel/cannonlake: Clean up FSP chipset lockdown configurationFelix Singer2021-08-121-27/+12
* soc/intel/cannonlake: Disable `TccOffsetClamp` if no offset is givenNico Huber2021-08-041-0/+1
* soc/intel/*: Allow configuring 8254 timer via CMOSSean Rhodes2021-08-031-2/+5
* soc/intel: Refactor `xdci_can_enable()` functionAngel Pons2021-07-011-4/+1
* soc/intel/cannonlake: Use new IRQ moduleTim Wawrzynczak2021-06-291-0/+208
* soc/intel/cannonlake: Use devfn_disable() function for XDCISubrata Banik2021-06-231-7/+3
* soc/intel/cannonlake: Make use of is_devfn_enabled() functionSubrata Banik2021-06-161-50/+17
* soc/intel: Drop unused lpss functionsFurquan Shaikh2021-06-071-7/+0
* soc/intel/cannonlake: Deduplicate function declarationFelix Singer2021-04-201-5/+2
* soc/intel/cannonlake: Remove unnecessary functionFelix Singer2021-04-201-10/+3
* drivers/intel/fsp1_1,fsp2_0: Refactor logo displayKyösti Mälkki2021-02-091-2/+3
* soc/intel/cannonlake: Allow RP#1 usage for ClkSrcJeremy Soller2021-01-211-0/+2
* soc/intel/cnl: Allow setting PCIe subsystem IDs after FSP-SJeremy Soller2021-01-111-0/+47
* soc/intel/cannonlake: Change mainboard_silicon_init_params argumentPatrick Rudolph2020-12-171-2/+2
* soc/intel/{skl,cnl}: replace PM ACPI timer dt option by KconfigMichael Niewöhner2020-11-131-3/+2
* soc/intel/cannonlake: Fix memory corruptionsJohn Zhao2020-10-191-2/+2
* soc/intel: Configure PAVP at compile-timeBenjamin Doron2020-10-121-0/+2
* src/soc/intel: Drop unneeded empty linesElyes HAOUAS2020-09-211-1/+0
* soc/intel/cnl: Use the common code to set the PchPmPwrCycDurV Sowmya2020-09-211-120/+1
* soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by defaultMichael Niewöhner2020-09-061-11/+10
* soc/intel/cnl: Enable HECI3 depending on devicetreeFelix Singer2020-09-041-1/+2
* soc/intel/cnl: Configure FSP option PcieRpSlotImplementedNico Huber2020-08-231-0/+2
* soc/intel/cnl: Set Heci1Disable depending on devicetree configFelix Singer2020-08-071-1/+2
* soc/intel/cannonlake: Configure SataPwrOptEnable only if SATA is enabledFelix Singer2020-07-281-5/+1
* src: Update bare access to BOOL CONFIG_ vals to CONFIG()Martin Roth2020-07-261-3/+3
* soc/intel/cannonlake: Add configs for USB 3.1 Gen2 EV settingsJamie Chen2020-07-201-0/+30
* soc/intel/cannonlake: make satahotplug user configurable via devicetreeJonas Loeffelholz2020-07-011-0/+4
* soc/intel/cannonlake: Add PchPmPwrCycDur to chip optionsSridhar Siricilla2020-06-251-0/+127
* soc/intel/cannonlake: Add RP configuration settingsChristian Walter2020-06-021-1/+13
* cannonlake: update processor power limits configurationSumeet R Pawnikar2020-05-261-3/+6
* soc/intel/cannonlake: Add VrPowerDeliveryDesign to chip optionsChristian Walter2020-05-261-0/+4
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* soc/intel/cannonlake: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-061-13/+2
* soc: Remove copyright noticesPatrick Georgi2020-03-181-1/+0
* soc/intel/cannonlake: Set correct serirq modeJeremy Soller2020-03-171-0/+4
* soc/intel/cannonlake: Plumb TetonGlacierMode into dtEdward O'Callaghan2020-02-281-0/+3
* soc/intel/{cnl,icl}: Avoid static 8254 clock gating on S3 resumeSubrata Banik2020-02-261-1/+1
* {drivers,soc}/intel/fsp2_0: Move chipset specific logo handling to SoCWim Vervoorn2019-12-191-0/+7
* soc/intel/cannonlake: Disable USB2 PHY Power gatingSurendranath Gurivireddy2019-11-271-0/+3
* soc/intel/cannonlake: set FSP param to enable or skip GOPMichael Niewöhner2019-10-301-0/+6
* soc/intel/cannonlake: Fix FSP UPDs settings with disabled GBEKane Chen2019-10-221-1/+12
* soc/intel: Replace config_of_path() with config_of_soc()Kyösti Mälkki2019-10-021-2/+2
* soc/intel/cnl: Remove unnecessary FSP UPD “PchPwrOptEnable” usageSubrata Banik2019-09-121-1/+0
* soc/intel/cannonlake: Add config for sata devslp pad reset configurationAamir Bohra2019-09-121-0/+5
* soc/intel/cannonlake: Allow coreboot to handle SPI lockdownSubrata Banik2019-09-091-8/+6
* soc/intel/cannonlake: Add ability to disable Heci1Bora Guvendik2019-09-091-0/+3
* soc/intel/cannonlake: Add config to disable display audio codecAamir Bohra2019-08-261-0/+1
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