coreboot.git - Coreboot firmware sources

	Commit message (Expand)	Author	Age	Files	Lines
*	soc/intel: Drop aliases on MMCONF_BASE_ADDRESS	Kyösti Mälkki	2021-02-16	1	-3/+0
*	soc/intel: Drop ABOVE_4GB_MEM_BASE_SIZE and use cpu_phys_address_size()	Furquan Shaikh	2020-05-14	1	-2/+0
*	soc/intel/common/block/systemagent: Use TOUUD as base for MMIO above 4G	Furquan Shaikh	2020-05-14	1	-1/+0
*	treewide: Remove "this file is part of" lines	Patrick Georgi	2020-05-11	1	-1/+0
*	soc/intel/cannonlake: Use SPDX for GPL-2.0-only files	Angel Pons	2020-04-06	1	-13/+2
*	soc: Remove copyright notices	Patrick Georgi	2020-03-18	1	-2/+0
*	soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper	Subrata Banik	2020-01-10	1	-1/+4
*	Revert "soc/intel/cannonlake: Remove DMA support for PTT"	Jeremy Soller	2019-10-21	1	-0/+4
*	soc/intel: Replace UART_BASE() and friends with a Kconfig	Nico Huber	2019-06-03	1	-8/+0
*	soc/intel/cnl: Generate DMAR ACPI table	John Zhao	2019-04-18	1	-0/+9
*	soc/intel/common/block: Move common uart function to block/uart	Subrata Banik	2018-08-20	1	-2/+4
*	soc/intel/cannonlake: Remove DMA support for PTT	Subrata Banik	2018-06-22	1	-4/+0
*	soc/intel/cannonlake: Use common p2sb driver	Lijian Zhao	2017-10-27	1	-0/+3
*	soc/intel/cannonlake: Fix HECI error on reset	Lijian Zhao	2017-10-19	1	-1/+1
*	soc/intel/cannonlake: Add northbridge dsdt table	Lijian Zhao	2017-10-03	1	-0/+2
*	soc/intel/cannonlake: Perform dram top calculation based on HW registers	Subrata Banik	2017-09-01	1	-2/+3
*	soc/intel/cannonlake: Add support for all UART port index	Subrata Banik	2017-08-21	1	-2/+6
*	soc/intel/cannonlake: Add bootblock.c	Andrey Petrov	2017-07-02	1	-0/+79