summaryrefslogtreecommitdiffstats
path: root/src/soc/intel/cannonlake/include
Commit message (Expand)AuthorAgeFilesLines
* soc/intel/cannonlake: Add emmc/sdc port idLijian Zhao2018-02-221-0/+2
* soc/intel/cannonlake: Add provision to make CSME function disable in SMM modeSubrata Banik2018-02-221-0/+1
* src/soc: Fix various typosJonathan Neuschäfer2018-02-202-3/+3
* soc/intel/cannonlake: Add missing GPIO pin definitionsLijian Zhao2018-02-162-32/+133
* soc/intel/cannonlake: Add Pch iSCLK programmingLijian Zhao2018-02-111-0/+1
* src/soc/intel/cannonlake: Update C-state latency control limitsVaibhav Shankar2018-01-231-7/+7
* mainboard/intel/cannonlake_rvp: Add support for MAX98373 speaker ampN, Harshapriya2018-01-231-0/+1
* soc/intel/cannonlake: Add audio NHLT supportLijian Zhao2018-01-231-0/+43
* soc/intel/cannonlake: Remove redundent CNL CPUID macrosSubrata Banik2018-01-091-7/+1
* soc/intel/cannonlake: provide LPDDR4 memory initNick Vaccaro2018-01-071-0/+106
* soc/intel/cannonlake: Correct PMC/GPIO routing informationLijian Zhao2018-01-051-0/+10
* src/soc/intel/cannonlake: Add _PRW for CNViBora Guvendik2017-12-131-9/+13
* soc/intel/cannonlake: Add support for D0 steppingLijian Zhao2017-12-111-0/+1
* soc/intel/cannonlake: Add PCH ID support in bootblock/report_platform.cSubrata Banik2017-12-081-2/+0
* soc/intel/cannonlake: Fix DSX_CFG macro name for AC_PRESENTFurquan Shaikh2017-12-051-1/+1
* soc/intel/cannonlake: fix gpio pin numbersBora Guvendik2017-11-171-165/+169
* soc/intel/{cannonlake,skylake}: Add _soc_ prefix in spi soc routineSubrata Banik2017-11-111-22/+0
* sb and soc: Enforce correct offset of member "chromeos" in global_nvs_tJonathan Neuschäfer2017-11-041-0/+2
* soc/intel/cannonlake: Use common p2sb driverLijian Zhao2017-10-271-0/+3
* soc/intel/cannonlake: Add support for C state and P stateShaunak Saha2017-10-261-1/+1
* soc/intel/cannonlake: Fix HECI error on resetLijian Zhao2017-10-191-1/+1
* soc/intel/cannonlake: Use EBDA structure to store soc reserve memory sizeSubrata Banik2017-10-191-0/+1
* soc/intel/cannonlake: Update PCIE CLKREQ programingLijian Zhao2017-10-182-0/+12
* soc/intel/cannonlake: Add finalize functionLijian Zhao2017-10-181-0/+3
* soc/intel/cannonlake: Use EBDA area to store cbmem_top addressSubrata Banik2017-10-182-2/+24
* soc/intel/cannonlake: change gpio device nameBora Guvendik2017-10-031-1/+1
* soc/intel/cannonlake: add initial ASL methods for SCS, GPIOBora Guvendik2017-10-031-0/+2
* soc/intel/cannonlake: Add northbridge dsdt tableLijian Zhao2017-10-031-0/+2
* soc/intel/cannonlake: Fill the SMI usageLijian Zhao2017-10-032-10/+72
* soc/intel/cannonlake: Add lpc pci driverLijian Zhao2017-10-032-0/+129
* soc/intel/cannonlake: Add PMC pci driversLijian Zhao2017-09-201-0/+1
* src/soc/intel/cannonlake: Define USB configuration paramsPratik Prajapati2017-09-141-0/+114
* soc/intel/cannonlake: Add serialio device configLijian Zhao2017-09-131-0/+43
* soc/intel/cannonlake: Add common ACPI support for CNLLijian Zhao2017-09-134-3/+58
* soc/intel/cannonlake: Perform dram top calculation based on HW registersSubrata Banik2017-09-012-2/+6
* soc/intel/cannonlake: use __packedAaron Durbin2017-08-261-1/+2
* soc/intel/cannonlake: Init UPD params based on configPratik Prajapati2017-08-252-0/+11
* soc/intel/cannonlake: Define soc_intel_cannonlake_configPratik Prajapati2017-08-222-0/+107
* soc/intel/cannonlake: Enable common PMC code for CNLLijian Zhao2017-08-214-13/+259
* soc/intel/cannonlake: Add support for all UART port indexSubrata Banik2017-08-211-2/+6
* soc/intel/cannonlake: Add SPI flash controller driverLijian Zhao2017-08-171-0/+2
* soc/intel/cannonlake: Rectify LPC Lock Enable (LE) bit definitionSubrata Banik2017-08-151-1/+1
* soc/intel/cannonlake: Call into FSP siliconinitLijian Zhao2017-08-151-0/+28
* soc/intel/{cannonlake,skylake}: fix PCH_P2SB_EPMASK macroAaron Durbin2017-08-151-1/+1
* soc/intel/cannonlake: Remove unused systemagent registersSubrata Banik2017-08-141-58/+0
* soc/cannonlake: Enable SMM code for Cannon LakeBrandon Breitenstein2017-08-111-0/+17
* soc/intel/cannonlake: Add missing _PCH_DEV definitionsFurquan Shaikh2017-08-111-6/+21
* soc/intel/cannonlake: Add memory map supportLijian Zhao2017-08-071-0/+2
* soc/intel/cannonlake: Correct gpio definitionLijian Zhao2017-07-271-1/+1
* Fix files with multiple newlines at the end.Martin Roth2017-07-241-1/+0