| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | soc/intel/cannonlake: Fix UART2 serial log broken issue | Subrata Banik | 2017-12-14 | 1 | -10/+10 |
| * | soc/intel/cannonlake: Clean up UART code | Aamir Bohra | 2017-12-09 | 1 | -6/+47 |
| * | soc/intel/cannonlake: Add support for all UART port index | Subrata Banik | 2017-08-21 | 1 | -1/+1 |
| * | soc/intel/cannonlake: Add proper support to enable UART2 in 16550 mode | Subrata Banik | 2017-08-16 | 1 | -0/+17 |
| * | soc/intel/cannonlake: Add postcar stage support | Lijian Zhao | 2017-08-15 | 1 | -5/+5 |
| * | Revert "soc/intel/cannonlake: Add postcar stage support" | Martin Roth | 2017-07-21 | 1 | -4/+0 |
| * | soc/intel/cannonlake: Add postcar stage support | Lijian Zhao | 2017-07-21 | 1 | -0/+4 |
| * | soc/intel/cannonlake: Add UART initialization | Andrey Petrov | 2017-06-29 | 1 | -0/+67 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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