| Commit message (Expand) | Author | Age | Files | Lines |
* | fsp2_0: Gather Kconfig declarations | Nico Huber | 2020-04-05 | 1 | -3/+0 |
* | Trim `.acpi_fill_ssdt_generator` and `.acpi_inject_dsdt_generator` | Nico Huber | 2020-04-02 | 1 | -1/+1 |
* | intel/fsp2_0: Make FSP_USE_REPO a SoC opt-in | Johanna Schander | 2020-03-30 | 1 | -0/+3 |
* | soc/intel/cometlake: Use IntelFSP repo | Felix Singer | 2020-03-25 | 1 | -1/+2 |
* | soc/intel/cfl/vr_config: Add 8-core desktop CPU support | Patrick Rudolph | 2020-03-23 | 1 | -0/+2 |
* | soc: Remove copyright notices | Patrick Georgi | 2020-03-18 | 89 | -146/+0 |
* | soc/intel/cannonlake: Set correct serirq mode | Jeremy Soller | 2020-03-17 | 3 | -4/+10 |
* | soc/intel/*/smihandler: Only compile in TCO SMI handler if needed | Patrick Georgi | 2020-03-12 | 1 | -0/+2 |
* | soc/intel: fix eist enabling | Matt Delco | 2020-03-10 | 1 | -1/+2 |
* | intel/soc: skl,apl,cnl,icl,tgl: add INTRUDER relevant registers | Michael Niewöhner | 2020-03-07 | 1 | -0/+5 |
* | intel/soc: skl,apl,cnl,icl,tgl,common: enable TCO SMIs if selected | Michael Niewöhner | 2020-03-07 | 1 | -1/+1 |
* | soc/intel/cpu: Select NO_FIXED_XIP_ROM_SIZE | Arthur Heymans | 2020-03-04 | 1 | -1/+0 |
* | src: capitalize 'PCIe' | Elyes HAOUAS | 2020-03-04 | 1 | -1/+1 |
* | soc/intel/{common, skl, cnl, apl}: Move print_me_fw_version() to CSE lib | Sridhar Siricilla | 2020-03-02 | 1 | -79/+1 |
* | soc/intel/cannonlake: Plumb TetonGlacierMode into dt | Edward O'Callaghan | 2020-02-28 | 2 | -0/+6 |
* | soc/intel/{cnl,icl}: Avoid static 8254 clock gating on S3 resume | Subrata Banik | 2020-02-26 | 1 | -1/+1 |
* | soc/intel/common/block: Move cse common functions into block/cse | Subrata Banik | 2020-02-25 | 1 | -39/+1 |
* | soc/intel/common/block: Move smihandler common functions into common code | Subrata Banik | 2020-02-25 | 1 | -40/+3 |
* | soc/intel/cannonlake: Add TDC config for CML | Marx Wang | 2020-02-25 | 2 | -0/+113 |
* | soc/intel/cnl: Rename hfsts into me_hfsts | Sridhar Siricilla | 2020-02-24 | 1 | -16/+11 |
* | src/intel: Define HFSTS3 register | Sridhar Siricilla | 2020-02-17 | 1 | -0/+14 |
* | soc/intel/{cnl,icl,skl,tgl}/bootblock: Update text for DMI PCR 2774 | Wim Vervoorn | 2020-02-17 | 1 | -2/+2 |
* | soc/intel{cnl,icl,skl,tgl}/bootblock: Make sure DMI PCR 2770 is set | Wim Vervoorn | 2020-02-17 | 1 | -0/+5 |
* | vboot: remove VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT option | Joel Kitching | 2020-02-17 | 1 | -1/+0 |
* | soc/intel/{cnl,icl,skl,tgl,common}: Make changes to send_heci_reset_req_messa... | Sridhar Siricilla | 2020-02-09 | 1 | -1/+1 |
* | soc/intel/{common,skl,cnl,icl,apl,tgl}: Move HFSTS1 register definition to SoC | Sridhar Siricilla | 2020-02-09 | 1 | -0/+28 |
* | soc/intel: Add get_pmbase | Eugene Myers | 2020-02-04 | 2 | -0/+9 |
* | soc/intel/cannonlake: Allow Audio DSP OSC qualification for low power idle | Aamir Bohra | 2020-02-04 | 3 | -1/+16 |
* | soc/intel: Remove duplicate CPUID entry | Subrata Banik | 2020-02-04 | 1 | -1/+1 |
* | soc/intel/cannonlake/bootblock: Add CML-S 2/4-Core MCH IDs | Gaggery Tsai | 2020-01-18 | 1 | -0/+2 |
* | soc/intel/cannonlake: Add chip config for SATA strength | Jamie Chen | 2020-01-18 | 3 | -0/+59 |
* | soc/intel/{cnl,icl,skl, tgl}: Move SOC_INTEL_COMMON_BLOCK_THERMAL into SoC sp... | Subrata Banik | 2020-01-16 | 1 | -0/+1 |
* | soc/intel/cannonlake: Fix ASL compilation remarks | Subrata Banik | 2020-01-14 | 2 | -8/+4 |
* | soc/intel/{apl,cnl,icl,skl,tgl}: Make above 4GB MMIO resource proper | Subrata Banik | 2020-01-10 | 2 | -2/+8 |
* | sb/intel/common: Add smbus_set_slave_addr() | Kyösti Mälkki | 2020-01-09 | 1 | -4/+0 |
* | soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpi | Subrata Banik | 2020-01-09 | 1 | -324/+0 |
* | soc/intel/cannonlake: Add VR config for CML | Jamie Chen | 2020-01-08 | 2 | -0/+144 |
* | soc/intel/cannonlake: Add Comet Lake H SA 4+2 Device ID | Jamie Chen | 2020-01-08 | 1 | -0/+1 |
* | soc/intel/{apl,cnl,icl,skl,tgl}: Clean up SA ASL code | Subrata Banik | 2020-01-07 | 1 | -205/+191 |
* | soc/intel/cannonlake: Add VR config for CFL, CNL and WHL | Patrick Rudolph | 2020-01-06 | 2 | -17/+266 |
* | soc/intel/{icl,cnl,tgl}: Always add PM1_TMR block to FADT | Meera Ravindranath | 2019-12-31 | 1 | -10/+8 |
* | soc/intel/cannonlake: Move GPIO PM configuration to soc level | Eric Lai | 2019-12-26 | 2 | -0/+58 |
* | soc/intel/cannonlake: Clean up report_cpu_info() function | Usha P | 2019-12-26 | 1 | -24/+4 |
* | soc/intel/cannonlake: Refactor pch_early_init() code | Usha P | 2019-12-26 | 7 | -13/+35 |
* | {drivers,soc}/intel/fsp2_0: Move chipset specific logo handling to SoC | Wim Vervoorn | 2019-12-19 | 2 | -0/+8 |
* | src/soc/intel: Remove unused <stdlib.h> | Elyes HAOUAS | 2019-12-19 | 3 | -3/+0 |
* | src: Use '#include <smp/node.h>' when appropriate | Elyes HAOUAS | 2019-12-19 | 1 | -0/+1 |
* | soc/intel{cannonlake,icelake}/northbridge.asl: Correct flash range | Wim Vervoorn | 2019-12-17 | 1 | -1/+1 |
* | src/soc/intel/cannonlake: Bump MAX_CPU from 8->12 | Edward O'Callaghan | 2019-12-16 | 1 | -0/+4 |
* | 3rdparty/fsp: Update to current master again | Nico Huber | 2019-12-16 | 1 | -0/+1 |