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* soc/intel: Add Raptor Lake device IDsBora Guvendik2022-05-161-0/+1
* soc/intel/common: Use mp_run_on_all_cpus_synchronously for APs MTRR initKane Chen2022-05-161-1/+2
* soc/intel: Remove unused <cpu/intel/common/common.h>Elyes HAOUAS2022-05-161-1/+0
* soc/intel/alderlake: Add new CPU IDLean Sheng Tan2022-04-041-0/+1
* soc/intel/alderlake: Update CPU IDs with correct steppingsLean Sheng Tan2022-04-041-4/+4
* arch/x86/postcar: Use a separate stack for C executionArthur Heymans2022-04-011-1/+1
* soc/intel/common/block/cpu: Enable ROM caching in ramstageSubrata Banik2022-03-171-0/+9
* soc/intel/common: Include Meteor Lake device IDsWonkyu Kim2022-03-091-0/+2
* soc/intel/apl: Rework on CPU privilege level implementationSubrata Banik2022-01-111-13/+0
* soc/intel/common: Add missing space before }Paul Menzel2022-01-101-1/+1
* soc/intel/common/block/cpu/car/exit_car_fsp.S: Align stackArthur Heymans2021-12-131-0/+2
* soc/intel/common: Refactor cpu_set_p_state_to_max_non_turbo_ratioSridhar Siricilla2021-12-061-3/+2
* soc/intel/common: Add CPU related APIsSridahr Siricilla2021-12-061-0/+53
* soc/intel/common: Include Alder Lake-N device IDsUsha P2021-11-291-0/+1
* drivers/fsp: Rewrite post code hex values in lowercaseSean Rhodes2021-11-181-1/+1
* cpu/x86/mp_init: use cb_err as status return type in remaining functionsFelix Held2021-10-221-1/+1
* soc/intel/*: only enable PM Timer emulation if the PM Timer is disabledMichael Niewöhner2021-10-171-1/+1
* src/soc to src/superio: Fix spelling errorsMartin Roth2021-10-051-1/+1
* soc/intel/common: round PM Timer emulation frequency multiplierMichael Niewöhner2021-10-021-1/+2
* soc/intel/alderlake: Add CPU ID 0x906a4Meera Ravindranath2021-09-301-0/+1
* soc/intel/{common,tgl,adl}: guard TME Kconfig option by SoC supportMichael Niewöhner2021-09-201-0/+7
* soc/intel: Add TGL-H CPUIDJeremy Soller2021-08-241-0/+1
* soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS KconfigSubrata Banik2021-08-163-0/+22
* soc/intel/common: Calculate and configure SF Mask 1Subrata Banik2021-08-151-11/+19
* soc/intel/common: Calculate and configure SF Mask 2Subrata Banik2021-08-152-0/+33
* soc/intel/common/cpu: Handle non-zero BSP APIC ID in init_cpusMAULIK V VAGHELA2021-08-091-2/+13
* soc/intel/common/block: Add space before comment delimiterSubrata Banik2021-07-241-1/+1
* src: use mca_clear_status function instead of open codingFelix Held2021-07-141-4/+1
* soc/intel/common: Use SPR for backing up data way and eviction maskSubrata Banik2021-07-141-6/+6
* soc/intel/common/block/cpu/cpulib: use mca_get_bank_count()Felix Held2021-07-141-3/+1
* include/cpu/x86/msr: introduce IA32_MC_*(x) macrosFelix Held2021-07-141-2/+2
* soc/intel/cache_as_ram.S: Fix CAR issues with BootguardArthur Heymans2021-06-261-0/+17
* soc/intel/cache_as_ram.S: Fix SOC_INTEL_APOLLOLAKEArthur Heymans2021-06-242-0/+10
* soc/intel/cache_as_ram.S: Add macro to detect bootguard nemArthur Heymans2021-06-241-6/+14
* soc/intel/car: Add support for bootguard CARArthur Heymans2021-06-221-0/+28
* soc/intel/common/cache_as_ram.S: Add macro to clear CARArthur Heymans2021-06-221-20/+22
* soc/intel/common/cache_as_ram.S: Add macro to find a free MTRRArthur Heymans2021-06-221-6/+44
* soc/intel/car/cache_as_ram.S: Fix typo in commentArthur Heymans2021-06-181-1/+1
* soc/intel/{common,alderlake}: Use generic name "Alderlake Platform"Sridhar Siricilla2021-06-111-3/+3
* soc/intel/alderlake: Update CPU and IGD Device IDsMaulik V Vaghela2021-05-141-0/+1
* drivers/intel/fsp2_0: Fix the FSP-T positionArthur Heymans2021-05-051-10/+1
* soc/intel/common,skl: set MSR LT_LOCK_MEMORY once, not per threadMichael Niewöhner2021-04-221-1/+1
* soc/intel/block/cpu/mp_init.c: Remove weak functionsArthur Heymans2021-03-181-11/+0
* soc/intel/common/block/cpu: Use tab instead of spaceSubrata Banik2021-03-111-9/+9
* soc/intel/common/block/cpu: Use tab instead of spaceSubrata Banik2021-03-051-3/+3
* soc/intel: Factor out common smmrelocate.cAngel Pons2021-03-033-0/+255
* intel/common/block/cpu: Add APIs to get CPU info from lapic IDAamir Bohra2021-02-231-0/+69
* intel: Rename config FSP_USES_MP_SERVICES_PPI to MP_SERVICES_PPIFurquan Shaikh2021-02-061-1/+1
* intel: Drop FSP_PEIM_TO_PEIM_INTERFACEFurquan Shaikh2021-02-061-2/+1
* soc/intel/*: Get rid of custom microcode cachingPatrick Rudolph2021-02-011-15/+4
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