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* soc: Add SPDX license headers to Kconfig filesMartin Roth2024-02-181-0/+2
| | | | | | | | | | Change-Id: Ie7bc4f3ae00bb9601001dbb71e7c3c84fd4f759a Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80596 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel: Unify the definition of TCO registersMarek Maslanka2024-01-301-2/+2
| | | | | | | | | | | | | | | | Move the definition of the TCO registers used in most boards to a separate file and use it consistently. Do not unify TCO for older incompatible platforms. BUG=b:314260167 TEST=none Change-Id: Id64a635d106cea879ab08aa7beca101de14b1ee6 Signed-off-by: Marek Maslanka <mmaslanka@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Jakub Czapiga <czapiga@google.com>
* soc/intel: Rename Makefiles from .inc to .mkMartin Roth2024-01-241-0/+0
| | | | | | | | | | | | | | | | | | The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ib479b93b7d0b2e790d0495b6a6b4b4298a515d9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/80073 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cmn/block/smm: Clear SPI SYNC_SS before disabling WPDSubrata Banik2023-12-221-2/+6
| | | | | | | | | | | | | | | | | | This patch follows the BWG recommendation (doc 729123) by clearing the SPI SYNC_SS bit before disabling the WPD bit in SPI_BIOS_CONTROL. This prevents boot hangs due to a 3-strike error. Unable to follow this guideline would result into boot hang (3-strike error). BRANCH=firmware-rex-15709.B TEST=Able to build and boot google/rex. Change-Id: I18dbbc92554d803eea38ceb0b936a9da9191cb11 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
* soc/intel/common/block/oc_wdt: Add OC watchdog common blockMichał Żygowski2023-08-262-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add new block for handling overclocking watchdog. The watchdog is present since Skylake or maybe even earlier so it is safe to use with most of the microarchitectures utilizing intelblocks. The patch adds the common block for initializing and feeding the watchdog. Timeout is defined statically in Kconfig and should be set high enough by the board or SoC Kconfig to let the board boot with full memory training and avoid reset loops. Full training of 128GB DDR5 DIMM memory on AlderLake takes about 5 minutes. Newer SoCs with newer memory technologies and higher RAM capacity may take more. The default has been set to 10 minutes. The patch also adds support for feeding watchdog in driverless mode, i.e. it utilizies periodic SMI to reload the timeout value and restart the watchdog timer. This is optional and selectable by Kconfig option as well. If the option is not enabled, payload and/or software must ensure to keep feeding the watchdog, otherwise the platform will reset. TEST=Enable watchdog on MSI PRO Z690-A and see the platform resets after some time. Enable the watchdog in driverless mode and see the platform no longer resets and periodic SMI keeps feeding the watchdog. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ib494aa0c7581351abca8b496fc5895b2c7cbc5bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/68944 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* intel/cmn/smm: Introduce PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_BMichał Żygowski2023-06-151-0/+9
| | | | | | | | | | | | | | | | Certain chipsets/SoCs like Apollo Lake use GEN_PMCON_B for periodic SMI rate selection unlike other chipsets which use GEN_PMCON_A. Introduce new Kconfig option PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B to indicate the register difference. Based on Apollo Lake datasheet Vol. 3 Revision 005: https://cdrdv2.intel.com/v1/dl/getContent/334819 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I11241836ecc9066d323977b030686567c87ed256 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
* intel/common/block/smm: remove return statements from void functionsYuchen He2023-03-231-3/+3
| | | | | | | | | | | | | | | | To be consistent with other occurrences in soc/intel/common, remove the return statements of weak void funtions since they are not generally useful. Found by the linter. Signed-off-by: Yuchen He <yuchenhe126@gmail.com> Change-Id: I3fb8217cfcae65b5dc317458b59aa431f1ccdaef Reviewed-on: https://review.coreboot.org/c/coreboot/+/73866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb,sb,soc/intel: Drop useless IO trap handlersKyösti Mälkki2022-12-071-18/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | There are four requirements for the SMI to hit a printk() this commit now removes. Build must have DEBUG_SMI=y, otherwise any printk() is a no-op inside SMM. ASL must have a TRAP() with argument 0x99 or 0x32 for SMIF value. Platform needs to have IO Trap #3 enabled at IO 0x800. The SMI monitor must call io_trap_handler for IO Trap #3. At the moment, only getac/p470 would meet the above criteria with TRAP(0x32) in its DSDT _INI method. The ASL ignores any return value of TRAP() calls made. A mainboard IO trap handler should have precedence over a southbridge IO trap handler. At the moment we seem to have no cases of the latter to support, so remove the latter. Change-Id: I3a3298c8d9814db8464fbf7444c6e0e6ac6ac008 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70365 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* sb,soc/intel: Fix SMI handler IO trap data maskKyösti Mälkki2022-12-071-1/+1
| | | | | | | | | | | Shift is done in multiples of 8 (1 << 3) bits. It was fixed already for i82801ix/jx. Change-Id: I5e1c2b3bf4ba68f34eb43e59fe783d5cd6e0a39a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc: Add SPDX license headers to MakefilesMartin Roth2022-10-311-0/+1
| | | | | | | | Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic875708697f07b6dae09d27dbd67eb8b960749f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* device/mmio.h: Move readXp/writeXp helpers to device/mmio.hJianjun Wang2022-03-081-2/+2
| | | | | | | | | | | | These helpers are not architecture dependent and it might be used for different platform. Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Ic13a94d91affb7cf65a2f22f08ea39ed671bc8e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62561 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common: Remove GPIO PAD lock config override from mainboardSubrata Banik2022-02-041-15/+0
| | | | | | | | | | | | | | | | | | This patch removes mainboard capability to override GPIO PAD lock configuration using `mb_gpio_lock_config` override function as the variant GPIO pad configuration table is now capable of locking GPIO PADs. BUG=b:208827718 TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6769f51afaf79b007d4f199bccc532d6b1c4d435 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* soc/intel/common: add generic gpio lock mechanismNick Vaccaro2021-12-072-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | For added security, there are some gpios that an SoC will want to lock once initially configured, such as gpios attached to non-host (x86) controllers, so that they can't be recofigured at a later point in time by rogue code. Likewise, a mainboard may have some gpios connected to secure busses and/or devices that they want to protect from being changed post initial configuration. This change adds a generic gpio locking mechanism that allows the SoC to export a list of GPIOs to be locked down and allows the mainboard to export a list of GPIOs that it wants locked down once initialization is complete. Use the SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS Kconfig option to enable this feature. BUG=b:201430600 TEST='emerge-brya coreboot chromeos-bootimage', flash and verify brya0 boots successfully to kernel. Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Change-Id: I42979fb89567d8bcd9392da4fb8c4113ef427b14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58351 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/common: Add InSMM.STS supportAngel Pons2021-06-211-2/+25
| | | | | | | | | | | | | | | Tested on HP 280 G2, SMMSTORE v1 and v2 still work. Other tests: - If one does not set BIOS_CONTROL bit WPD, SMMSTORE breaks. - If one does not write the magic MSR `or 1`, SMMSTORE breaks. Change-Id: Ia90c0e3f8ccf895bfb6d46ffe26750393dab95fb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* security/intel: Add option to enable SMM flash access onlyAngel Pons2021-06-211-27/+29
| | | | | | | | | | | | | | | | | | On platforms where the boot media can be updated externally, e.g. using a BMC, add the possibility to enable writes in SMM only. This allows to protect the BIOS region even without the use of vboot, but keeps SMMSTORE working for use in payloads. Note that this breaks flashconsole, since the flash becomes read-only. Tested on Asrock B85M Pro4 and HP 280 G2, SMM BIOS write protection works as expected, and SMMSTORE can still be used. Change-Id: I157db885b5f1d0f74009ede6fb2342b20d9429fa Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* soc/intel/common/block/smm: Add `mainboard_smi_finalize`Aseda Aboagye2021-06-191-0/+7
| | | | | | | | | | | | | | | | | This commit adds a method called `mainboard_smi_finalize` which provides a mechanism for a mainboard to execute some code as part of the finalize method in the SMM stage before SoC does its finalization. BUG=b:191189275 BRANCH=None TEST=Implement `mainboard_smi_finalize` on lalala and verify that the code executes in SMM. Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: If1ee63431e3c2a5831a4656c3a361229acff3f42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* soc/intel/common/block/smm: Drop stale commentAngel Pons2021-04-191-2/+0
| | | | | | | | | | This comment is most likely a copy-paste leftover from Braswell. Change-Id: I49bfa3cc56539df0b47d2e2bd74b2bfc45421034 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* soc/intel/common: Prevent SMI storm when setting SPI WPD bitAngel Pons2021-04-061-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From Skylake/Sunrise Point onwards, there are two BIOS_CNTL registers: one on the LPC/eSPI PCI device, and another on the SPI PCI device. When the WPD bit changes from 0 to 1 and the LE bit is set, the PCH raises a TCO SMI with the BIOSWR_STS bit set. However, the BIOSWR_STS bit is not set when the TCO SMI comes from the SPI or eSPI controller instead, but a status bit in the BIOS_CNTL register gets set. If the SMI cause is not handled, another SMI will happen immediately after returning from the SMI handler, which results in a deadlock. Prevent deadlocks by clearing the SPI synchronous SMI status bit in the SMI handler. When SPI raises a synchronous SMI, the TCO_STS bit in the SMI_STS register is continously set until the SPI synchronous SMI status bit is cleared. To not risk missing any other TCO SMIs, do not clear the TCO_STS bit again in the same SMI handler invocation. If the TCO_STS bit remains set when returning from SMM, another SMI immediately happens and clears the TCO_STS bit, handling any pending events. SPI can also generate asynchronous SMIs when the WPD bit is cleared and one attempts to write to flash using SPI hardware sequencing. This patch does not account for SPI asynchronous SMIs, because they are disabled by default and cannot be enabled once the BIOS Interface Lock-Down bit in the BIOS_CNTL register has been set, which coreboot already does. These asynchronous SMIs set the SPI_STS bit of the SMI_STS register. Clearing the SPI asynchronous SMI source should be done inside the SPI_STS SMI handler, which is currently not implemented. All of this goes out of the scope of this patch, and is currently not necessary anyway. This patch does not handle eSPI because I cannot test it, and knowing if a board uses LPC or eSPI from common code is currently not possible, and this is beyond the scope of what this commit tries to achieve (fix SPI). Tested on HP 280 G2, no longer deadlocks when SMM BIOS write protection is on. Write protection will be enforced in a follow-up. Change-Id: Iec498674ae70f6590c33a6bf4967876268f2b0c8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50754 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common/block/smm: Ignore PM1 and GPE0 events in SCI modeAngel Pons2021-03-101-14/+6
| | | | | | | | | | | | | | | | | | | When the SCI_EN bit is set, PM1 and GPE0 events will trigger a SCI instead of a SMI#. However, SMI_STS bits PM1_STS and GPE0_STS can still be set. Therefore, when SCI_EN is set, ignore PM1 and GPE0 events in the SMI# handler, as these events have triggered a SCI. Do not ignore any other SMI# types, since they cannot cause a SCI. Note that these bits are reserved on APL and GLK. However, SoC-specific code already accounts for it. Thus, no special handling is needed here. Change-Id: I5998b6bd61d796101786b57f9094cdaf0c3dfbaa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* sb,soc/intel: Remove no-op APMC for C-state and P-stateKyösti Mälkki2021-01-251-14/+0
| | | | | | | | Change-Id: I3c1aa7f68eb03f04ddb9c1a5e960e3e2050a029c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49250 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/x86/smm: Use common APMC loggingKyösti Mälkki2021-01-251-7/+1
| | | | | | | | | | Unify the debug messages on raised SMIs. Change-Id: I34eeb41d929bfb18730ac821a63bde95ef9a0b3e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49248 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86: Pass GNVS as parameter to SMM moduleKyösti Mälkki2021-01-041-21/+0
| | | | | | | | Change-Id: I9d7417462830443f9c96273d2cc326cbcc3b17dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48698 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common/block/smm/smihandler: Fix compilation under x86_64Patrick Rudolph2020-12-011-2/+2
| | | | | | | | | Change-Id: Ie44ded11a6a9ddd2a1163d2f57dad6935e1ea167 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/common/block/smm: Fix compilation without intel uart codePatrick Rudolph2020-10-121-2/+2
| | | | | | | | | | | Allow to link the smihandler when not selecting SOC_INTEL_COMMON_BLOCK_UART. Change-Id: Iabca81c958d00c48e0616579cbba61d254c5eb68 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
* src/soc/intel: Drop unneeded empty linesElyes HAOUAS2020-09-211-1/+0
| | | | | | | | Change-Id: Id93aab5630e928ee4d7e957801e15a4cc8739fae Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44594 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* SMM: Validate more user-provided pointersPatrick Rudolph2020-08-211-0/+4
| | | | | | | | | | | | | | | Mitigate issues presented in "Digging Into The Core of Boot" found by "Yuriy Bulygin" and "Oleksandr Bazhaniuk" at RECON-MTL-2017. Validate user-provided pointers using the newly-added functions. This protects SMM from ring0 attacks. Change-Id: I8a347ccdd20816924bf1bceb3b24bf7b22309312 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* ACPI GNVS: Replace uses of smm_get_gnvs()Kyösti Mälkki2020-07-012-10/+0
| | | | | | | | Change-Id: I7b657750b10f98524f011f5254e533217fe94fd8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* ACPI: Drop typedef global_nvs_tKyösti Mälkki2020-06-302-5/+5
| | | | | | | | | | | | Bring all GNVS related initialisation function to global scope to force identical signatures. Followup work is likely to remove some as duplicates. Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ACPI: Replace smm_setup_structures()Kyösti Mälkki2020-06-241-19/+0
| | | | | | | | | | | | | | Except for whitespace and varying casts the codes were the same when implemented. Platforms that did not implement this are tagged with ACPI_NO_SMI_GNVS. Change-Id: I31ec85ebce03d0d472403806969f863e4ca03b6b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/intel/common: Replace smm_soutbridge_enable(SMI_FLAGS)Kyösti Mälkki2020-06-161-1/+11
| | | | | | | | Change-Id: I8c4dc5ab91891de9737189bd7ae86df18d86f758 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* src: Remove unused 'include <bootstate.h>'Elyes HAOUAS2020-06-021-1/+0
| | | | | | | | Change-Id: I54eda3d51ecda77309841e598f06eb9cea3babc1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-113-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common: Fix 16-bit read/write PCI_COMMAND registerElyes HAOUAS2020-05-011-4/+4
| | | | | | | | Change-Id: I09cc69a20dc67c0f48b35bfd2afeaba9e2ee5064 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* soc/intel/common: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-063-39/+6
| | | | | | | | | | Done with sed and God Lines. Only done for C-like code for now. Change-Id: Ic5a920bfe1059534566ceab85a97219dd56f069e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40213 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc: Remove copyright noticesPatrick Georgi2020-03-183-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I4c110f60b764c97fab2a29f6f04680196f156da5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* soc/intel/common/block/smm: add case intrusion to SMI handlerMichael Niewöhner2020-03-111-0/+9
| | | | | | | | | | | | | | | | | | | | | This adds case intrusion detection to the SMI handler. At this point one can add the code to be executed when the INTRUDER signal gets asserted (iow: when the case is opened). Examples: - issue a warning - trigger an NMI - call poweroff() - ... Tested on X11SSM-F. Change-Id: Ifad675bb09215ada760efebdcd915958febf5778 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* intel/soc: skl,apl,cnl,icl,tgl,common: enable TCO SMIs if selectedMichael Niewöhner2020-03-071-1/+4
| | | | | | | | | | | | | Enable TCO SMIs in common code, if selected by Kconfig. This is needed for the follow-up commits regarding INTRUDER interrupt. Tested on X11SSM-F. Change-Id: If63effe74ac59b5d051a6454bc6375bb89605215 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/intel/common/block/smm: add Kconfig for TCO SMIMichael Niewöhner2020-03-071-0/+6
| | | | | | | | | | | Allow the user to select if TCO shall issue SMIs or not. Change-Id: Id22777e9573376e5a079a375400caa687bc41afb Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39326 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common/block: Move smihandler common functions into common codeSubrata Banik2020-02-251-9/+33
| | | | | | | | | | | | | | This patch cleans soc/intel/{apl/cnl/skl/icl/tgl} by moving common soc code into common/block/smihandler.c BUG=b:78109109 TEST=Build and boot KBL/CNL/APL/ICL/TGL platform. Change-Id: Ic082bc5d556dd19617d83ab86f93a53574b5bc03 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* src/soc/intel: Remove unused <stdlib.h>Elyes HAOUAS2019-12-191-1/+0
| | | | | | | | Change-Id: I71a5a6c3748d5a3910970bfb1ec3d7ecd3184cfd Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33686 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ELOG: Introduce elog_gsmi variantsKyösti Mälkki2019-11-091-4/+3
| | | | | | | | | | This avoids a lot of if (CONFIG(ELOG_GSMI)) boilerplate. Change-Id: I87d25c820daedeb33b3b474a6632a89ea80b0867 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36647 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common/smm: Add missing printk statementTim Wawrzynczak2019-08-211-0/+1
| | | | | | | | | | | | | SMI trap handler was missing a printk statement, which caused Coverity to flag "data &= mask;" as a redundant operation. Change-Id: I71da74e5e08e7d7e6d61c1925db19324efd73f0a Found-by: Coverity CID 1381621 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
* soc/intel: Rename some SMM support functionsKyösti Mälkki2019-08-151-1/+1
| | | | | | | | | | | Rename southbridge_smm_X to smm_southbridge_X. Rename most southcluster_smm_X to smm_southbridge_X. Change-Id: I4f6f9207ba32cf51d75b9ca9230e38310a33a311 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34856 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/x86: Separate save_state struct headersKyösti Mälkki2019-08-131-0/+2
| | | | | | | | | | | Any platform should need just one of these. Change-Id: Ia0ff8eff152cbd3d82e8b372ec662d3737078d35 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34820 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel: Drop pmc_soc_restore_power_failure()Nico Huber2019-08-091-1/+2
| | | | | | | | | | | | | | Get rid of this function and its dangerous, weak implementation. Instead, call pmc_set_power_failure_state() directly from the SMI handler. Change-Id: I0718afc5db66447c93289643f9097a4257b10934 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* arch/x86: Move TSEG_STAGE_CACHE implementationKyösti Mälkki2019-08-081-12/+0
| | | | | | | | | | | This is declared weak so that platforms that do not have smm_subregion() can provide their own implementation. Change-Id: Ide815b45cbc21a295b8e58434644e82920e84e31 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* intel/apollolake: Replace smm_region_info() with smm_region()Kyösti Mälkki2019-08-071-6/+0
| | | | | | | | | | Implementation remains the same. Change-Id: I8483bb8e5bba66b4854597f58ddcfe59aac17ae0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* cpu/x86/smm: Promote smm_subregion()Kyösti Mälkki2019-08-071-1/+0
| | | | | | | | | | | | No need to limit these declarations to FSP. Both PARALLEL_MP_INIT smm_relocate() and TSEG_STAGE_CACHE can be built on top of this. Change-Id: I7b0b9b8c8bee03aabe251c50c47dc42f6596e169 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* drivers/intel: Move FSP stage_cache implementation into common blockSubrata Banik2019-07-091-0/+13
| | | | | | | | Change-Id: Iebb6d698c236a95162b3c7eb07987483a293b50a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* soc/intel/{cml, whl}: Add option to skip HECI disable in SMMSubrata Banik2019-06-131-0/+8
| | | | | | | | | | | | | | | | | | | | This patch provides an additional option to skip HECI function disabling using SMM mode for WHL and CML platform, where FSP has dedicated UPD to make HECI function disable. User to select HECI_DISABLE_USING_SMM if FSP doesn't provided dedicated UPD. Right now CNL and ICL platform will use HECI_DISABLE_USING_SMM kconfig to make HECI disable and WHL/CML has to rely on FSP to make HECI disable. Change-Id: If3b064f3c32877235916f966a01beb525156d188 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-29 23:58:50 +0000