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This patch moves common thermal API between chipsets
with thermal device as PCI device and thermal device behind PMC
into common file (thermal_common.c).
Introduce CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV to let SoC
Kconfig to select as applicable for underlying chipset.
+------------------------------------------------------+--------------+
| Thermal Kconfig | SoC |
+------------------------------------------------------+--------------+
| CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV | SKL/KBL, CNL |
| | till ICL |
+------------------------------------------------------+--------------+
| CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC | TGL onwards |
| | ICL |
+------------------------------------------------------+--------------+
Either of these two Kconfig internally selects
CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL to use common thermal APIs.
BUG=b:193774296
TEST=Able to build and boot hatch and adlrvp platform.
Change-Id: I14df5145629ef03f358b98e824bca6a5b8ebdfc6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Thermal configuration has evolved over PCH generations where
latest PCH has provided an option to allow thermal configuration
using PMC PWRMBASE registers.
This patch adds an option for impacted SoC to select the Kconfig
for allowing thermal configuration using PMC PCH MMIO space.
BUG=b:193774296
TEST=Able to build and boot hatch and adlrvp platform.
Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570a0
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59209
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch ensures IA common thermal block is now able to compile
under romstage with necessary compilation issues fixed.
BUG=b:193774296
Change-Id: I3279f55436977ab9a47e04455d8469e50b5c33c8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59391
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown
when S0ix is enabled.
BUG=None
BRANCH=None
TEST=Verified Thermal Device (B0: D18: F0) TSPM offset 0x1c [LTT (8:0)]
value is 0xFE.
Change-Id: Ibd1e669fcbfe8dc6e6e5556aa5b1373ed19c3685
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33129
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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