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* soc/intel: transition full control over PM Timer from FSP to corebootMichael Niewöhner2021-10-171-0/+9
| | | | | | | | | | | | | | | | | | | Set `EnableTcoTimer=1` in order to keep FSP from 1) enabling ACPI Timer emulation in uCode. 2) disabling the PM ACPI Timer. Both actions are now done in coreboot. `EnableTcoTimer=1` makes FSP skip these steps in any possible case including `SkipMpInit=0`, `SkipMpInit=1`, use of the MP PPI or FSP Multiphase Init. This way full control is left to coreboot. Change-Id: I8005daed732c031980ccc379375ff5b09df8dac1 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lance Zhao
* soc/intel: implement ACPI timer disabling per SoC and drop common codeMichael Niewöhner2021-10-172-2/+1
| | | | | | | | | | | Since it's just a one-liner, implement disabling of the ACPI timer in soc code. This reduces complexity. Change-Id: I434ea87d00f6e919983d9229f79d4adb352fbf27 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* soc/intel: move disabling of PM Timer to SoC PMC codeMichael Niewöhner2021-10-172-9/+9
| | | | | | | | | | | | | | | | | | | | Move disabling of PM Timer to SoC PMC code. The original reason for placing that in `finalize` [1] was FSP hanging due to use of the PM timer without enabling timer emulation first in coreboot, which was added later [2]. [1] commit 6c1bf27dae (intel/skylake: disable ACPI PM Timer to enable XTAL OSC shutdown) [2] commit f004f66ca7 (soc/intel/skylake: Enable ACPI PM timer emulation on all CPUs) Change-Id: I354c3aea0c8c1f8ff3d698e0636932b7b76125f7 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* soc/intel: deduplicate acpi_fill_soc_wakeMichael Niewöhner2021-10-171-15/+0
| | | | | | | | | | | | The PM1_EN bits WAK_STS, RTC_EN, PWRBTN_EN don't need any SoC-specific handling. Deduplicate `acpi_fill_soc_wake` by setting these bits in common code. Change-Id: I06628aeb5b82b30142a383b87c82a1e22a073ef5 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* soc/intel: drop P_BLK supportMichael Niewöhner2021-10-131-3/+0
| | | | | | | | | | | | | | P_BLK is legacy and superseded by ACPI _CST. Also, the implementation for most platforms in soc/intel is broken. Thus, drop it. For APL the IO redirection is kept since it's used as replacement for the broken MWAIT instructions. Change-Id: I489aa7886dd9a4c1e6c12542bc2a1feba245ec36 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* soc/intel: replace dt option PmTimerDisabled by KconfigMichael Niewöhner2021-10-123-12/+3
| | | | | | | | | | | | | | | | | | Replace the dt option `PmTimerDisabled` with use of the Kconfig option `USE_PM_ACPI_TIMER` for enabling/disabling the PM Timer. A default value representing the prior devicetree value was added to the boards system76/{lemp10,galp5,darp7}, so this change will not alter behaviour. Change-Id: If1811c6b98847b22272acfa35ca44f4fbca68947 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* soc/intel/*/cpu.c: Add missing space in commentAngel Pons2021-10-121-1/+1
| | | | | | | | | | | | Add a space before the `*/` C-style comment ending. Change-Id: Ic8928286c8237808b9e380e4393078792589615d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* soc/intel: Drop unnecessary `select REG_SCRIPT`Angel Pons2021-09-291-1/+0
| | | | | | | | | | | | | These platforms no longer use reg-script. Drop unneeded select. Change-Id: I8fc4dc29d25dffbf9ed1947d0ff013b2fae0faaf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/{cnl,jsl,tgl,ehl,adl}: rename PMC device init/enable callbacksMichael Niewöhner2021-09-291-4/+4
| | | | | | | | | | | | | The current names of the PMC init/enable callbacks are very confusing. Rename them. Change-Id: I69f54f3b4e1ea9a9b4fa5c8dd9c0d454d7cd1283 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/{xeon-sp,icl,tgl,jsl,ehl}: add NMI_{EN,STS} registersMichael Niewöhner2021-09-232-0/+12
| | | | | | | | | | | | | | | | | | | Add NMI_EN and NMI_STS registers, so NMI interrupts can be used. References: - XEON-SP: Intel doc# 633935-005 and 547817 rev1.5 - ICL-LP: Intel doc# 341081-002 - TGL-LP: Intel doc# 631120-001 - TGL-H: Intel doc# 636174-002 - JSL: Intel doc# 634545-001 - EHL: Intel doc# 636722-002 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I2621f4495dfd4f95f9774d9081e44c604de830a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lance Zhao
* soc/intel/elkhartlake: Clear RTC_BATTERY_DEADTim Wawrzynczak2021-09-201-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | | Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS and backed up to flash (RW_NVRAM). However, on the very first boot after a flash of the full SPI image (so RW_NVRAM is empty), if RTC_BATTERY_DEAD is set, coreboot persistently requests recovery before FSP-M finishes (which appears to be the current location that RTC_BATTERY_DEAD is cleared on this platform). This is because vbnv_cmos_failed() will still return 1. Therefore, immediately after reading RTC_BATTERY_DEAD, it is cleared. This prevents an infinite boot loop when trying to set the recovery mode bit. Note that this was the behavior for previous generations of Intel PMC programming as well (see southbridge/intel, soc/skylake, soc/broadwell, etc). BUG=b:181678769 Change-Id: I95753fa536fae8ca4bb95007419875815c1bcb06 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* soc/intel/{ehl,jsl}: make use of Kconfig options for PRMRR sizeMichael Niewöhner2021-09-172-11/+4
| | | | | | | | | | | Migrate the last two platforms to using Kconfig through `get_valid_prmrr_size()` instead of hardcoded values in the devicetree. Change-Id: I93aa177f741ca8b2a2d50fae2515606b96784e83 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/elkhartlake: Switch to runtime generation of Power EngineTim Wawrzynczak2021-09-103-3/+11
| | | | | | | | | | | The pep.asl file is being obsoleted by runtime generation, therefore switch elkhartlake boards to this method. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I47f03b440729d4b37ae0abc84bd1d18c4e01657d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* cpu/x86/tsc: Deduplicate Makefile logicAngel Pons2021-09-081-1/+0
| | | | | | | | | | | | | | | | | The code under `cpu/x86/tsc` is only compiled in when its `Makefile.inc` is included from platform (CPU/SoC) code and the `UDELAY_TSC` Kconfig option is enabled. Include `cpu/x86/tsc/Makefile.inc` once from `cpu/x86/Makefile.inc` and drop the now-redundant inclusions from platform code. Also, deduplicate the `UDELAY_TSC` guards. Change-Id: I41e96026f37f19de954fd5985b92a08cb97876c1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57456 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/elkhartlake: Lock PAM registers in finalizeTim Wawrzynczak2021-09-052-0/+11
| | | | | | | | | | | | Use the support from the previous patch to have coreboot lock the PAM registers instead of the FSP when the lockdown configuration is set to coreboot. Change-Id: Ib6fce70d6b0386906850884880dadbf45597452d Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* acpi: Fill fadt->century based on KconfigNico Huber2021-08-191-1/+0
| | | | | | | | | Change-Id: I916f19e022633b316fbc0c6bf38bbd58228412be Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Move post_codes.h to commonlib/console/Ricardo Quesada2021-08-042-2/+2
| | | | | | | | | | | | | | | | | | | | | Move post_codes.h from include/console to commonlib/include/commonlib/console. This is because post_codes.h is needed by code from util/ (util/ code in different commit). Also, it sorts the #include statements in the files that were modified. BUG=b:172210863 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Change-Id: Ie48c4b1d01474237d007c47832613cf1d4a86ae1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56403 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/*: Allow configuring 8254 timer via CMOSSean Rhodes2021-08-031-1/+4
| | | | | | | | | | | | | | Currently, the `USE_LEGACY_8254_TIMER` Kconfig option is the only way to enable or disable the legacy 8254 timer. Add the `legacy_8254_timer` CMOS option to allow enabling and disabling the 8254 timer without having to rebuild and reflash coreboot. If options are not enabled or the option is missing in cmos.layout, the Kconfig setting is used. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic82c7f25cdf6587de5c40f59441579cfc92ff2f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* soc/intel/elkhartlake: Update UART clock divider paramsLean Sheng Tan2021-07-291-4/+4
| | | | | | | | | | | | As EHL UART source clock is 120MHz, update the clock divider parameters (M & N) to reflect the right value. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I30c21bc4d1ef901a318a12664b61be75c1acf23b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56422 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* src/*: Specify type of `CBFS_SIZE` onceAngel Pons2021-07-261-1/+0
| | | | | | | | | | | | | | | | There's no need to specify the type of the `CBFS_SIZE` Kconfig symbol more than once. This is done in `src/Kconfig`, along with its prompt. Change-Id: I9e08e23e24e372e60c32ae8cd7387ddd4b618ddc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56552 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common: Rename kconfig PMC_EPOCLean Sheng Tan2021-07-191-2/+2
| | | | | | | | | | | Rename PMC_EPOC to SOC_INTEL_COMMON_BLOCK_PMC_EPOC to maintain common naming convention. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: If8a264007bbb85a44bbdfa72115eb687c32ec36e Reviewed-on: https://review.coreboot.org/c/coreboot/+/55982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/elkhartlake: Expose FIVR config to mainboardLean Sheng Tan2021-07-172-11/+75
| | | | | | | | | | | | | | | | Elkhart Lake provides option to configure FIVR (Fully Integrated Voltage Regulators) via parameters in FSP-S. This CL removes fixed FIVR config values and expose these parameters to the devicetree so that they can be configured on mainboard level as needed. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Ie1b0e0cc908ba69805dec7682100dfccb3b9d8b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/elkhartlake: Make use of `cpu/intel/cpu_ids.h'Subrata Banik2021-07-172-2/+1
| | | | | | | | | | | | Remove inclusion of mp_init.h for getting CPUIDs and use dedicated cpu_ids.h file in SoC directory. Change-Id: Ieb8063116bee59f6f6bf1f6b0b2349ce22bd67bd Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
* src: Introduce `ARCH_ALL_STAGES_X86`Angel Pons2021-07-021-1/+0
| | | | | | | | | | | | | | | Introduce the `ARCH_ALL_STAGES_X86` Kconfig symbol to automatically select the per-stage arch options. Subsequent commits will leverage this to allow choosing between 32-bit and 64-bit coreboot where all stages are x86. AMD Picasso and AMD Cezanne are the only exceptions to this rule: they disable `ARCH_ALL_STAGES_X86` and explicitly set the per-stage arch options accordingly. Change-Id: Ia2ddbae8c0dfb5301352d725032f6ebd370428c9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* soc/intel: Refactor `xdci_can_enable()` functionAngel Pons2021-07-011-4/+1
| | | | | | | | | | | | The same pattern appears on all `xdci_can_enable()` call sites. Move the logic inside the function and take the xDCI devfn as parameter. Change-Id: I94c24c10c7fc7c5b4938cffca17bdfb853c7bd59 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/elkhartlake: Enable PCH GBELean Sheng Tan2021-06-305-3/+68
| | | | | | | | | | | | | | | | | | Enable PCH GBE with following changes: 1. Configure PCH GBE related FSP UPD flags 2. Use EHL own GBE ACPI instead of common code version due to different B:D.F from the usual GBE 3. Add kconfig PMC_EPOC to use the PMC XTAL read function Due to EHL GBE comes with time sensitive networking (TSN) capability integrated, EHL FSP is using 'PchTsn' instead of the usual 'PchLan' naming convention across the board. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I6b0108e892064e804693a34e360034ae7dbee68f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* src: Move `select ARCH_X86` to platformsAngel Pons2021-06-301-0/+1
| | | | | | | | | | | | To generalise the choice of 32-bit or 64-bit coreboot on x86 hardware, have platforms select `ARCH_X86` directly instead of through per-stage Kconfig options, effectively reversing the dependency order. Change-Id: If15436817ba664398055e9efc6c7c656de3bf3e4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* soc/intel: Drop casts around `soc_read_pmc_base()`Angel Pons2021-06-281-2/+1
| | | | | | | | | | | | | | | | | The `soc_read_pmc_base()` function returns an `uintptr_t`, which is then casted to a pointer type for use with `read32()` and/or `write32()`. But since commit b324df6a540d154cc9267c0398654f9142aae052 (arch/x86: Provide readXp/writeXp helpers in arch/mmio.h), the `read32p()` and `write32p()` functions live in `arch/mmio.h`. These functions use the `uintptr_t type for the address parameter instead of a pointer type, and using them with the `soc_read_pmc_base()` function allows dropping the casts to pointer. Change-Id: Iaf16e6f23d139e6f79360d9a29576406b7b15b07 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
* soc/intel/elkhartlake: Use is_devfn_enabled() for Device4Enable UPDSubrata Banik2021-06-231-3/+2
| | | | | | | | | | | | | | 1. Replace pcidev_path_on_root() and is_dev_enabled() functions combination with is_devfn_enabled() while enabling Thermal config. 2. Remove unused local variable of device structure type (struct device *). Change-Id: Icc2a44d6d3f1a78bf47354049dd9e2a0ed2282ba Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/elkhartlake: Use devfn_disable() function for XDCISubrata Banik2021-06-231-9/+3
| | | | | | | | | | | | | | | | | | | Use devfn_disable() for disabling a PCI device rather than using `dev->enabled = 0`. Also, use is_devfn_enabled() to get the device current state prior updating the FSP-S UPD for XDCI. TEST=FSP-S disabled XDCI when `xdci_can_enable` returns 0 and XDCI is disabled at PCI enumeration `PCI: 00:14.1: enabled 0`. Change-Id: I8ca0813e18da0f95eb9293b6d0bbdf933a1e7039 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55725 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/elkhartlake: Expose In-Band ECC config to mainboardWerner Zeh2021-06-212-0/+36
| | | | | | | | | | | | | | | Elkhart Lake provides a feature called "In-Band ECC" which uses a piece of system DRAM to store the ECC information in. There are a few parameters in FSP-M to set this feature up as needed. This patch adds code to expose these parameters to the devicetree so that they can be configured on mainboard level as needed. Change-Id: I7a4953d7b35277de01daff04211450e3d1bd8103 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55668 Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/elkhartlake: Make use of FSP_ARRAY_LOAD macroLean Sheng Tan2021-06-182-67/+15
| | | | | | | | | | | Use FSP_ARRAY_LOAD macro for checking and loading array type configs into array type UPDs to increase readability. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I2562977e55f8909038697f7e19b82ec6b5e47fae Reviewed-on: https://review.coreboot.org/c/coreboot/+/55553 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* soc/intel/elkhartlake: Make use of is_devfn_enabled()Subrata Banik2021-06-163-17/+8
| | | | | | | | | | | | | | | | | 1. Replace all pcidev_path_on_root() and is_dev_enabled() functions combination with is_devfn_enabled(). 2. Remove unused local variable of device structure type (struct device *). 3. Replace pcidev_path_on_root() and dev->enabled check with is_devfn_enabled() call. TEST=Able to build and boot without any regression seen on EHL. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: Iadf9145a11f27ff0e182f146b6fe5a01e6cf3ed8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/elkhartlake: Update FSP-S FuSa related settingsLean Sheng Tan2021-06-112-0/+11
| | | | | | | | | | | | Further add initial Silicon UPD settings for FuSa (Functional Safety). Disable all by default, due to FSP binary enable all by default. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I88264ba3e3f9f54ad949c55b230082d1fa289fa4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55342 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/elkhartlake: Update FSP-S PM & Thermal related configsLean Sheng Tan2021-06-112-0/+93
| | | | | | | | | | | Further add initial Silicon UPD settings for thermal and power management stuffs. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I04ded059c36f18925b7a74c934fef2566c3db8fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/55335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* soc/intel/elkhartlake: Fix gpio_soc_defs.h variable typoLean Sheng Tan2021-06-101-1/+1
| | | | | | | | | | Fix GPIO_COM2_END from GPIO_RSVD_2 to GPIO_RSVD_12. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I670f4bec8f141da73428010371754746a455df25 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55334 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/elkhartlake: Use FSP from FSP repo by defaultLean Sheng Tan2021-06-101-2/+5
| | | | | | | | | | | | | Select 'HAVE_INTEL_FSP_REPO' so that the FSP binary from the FSP repository is used by default. Also, use the FSP headers from the FSP repository instead. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I0c1bcb07ed0f73e1d5ada5f6f16b84816c4ef3d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55229 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/x86: Default to PARALLEL_MP selectedKyösti Mälkki2021-06-071-1/+0
| | | | | | | | Change-Id: I9833c4f6c43b3e67f95bd465c42d7a5036dff914 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/intel: Drop unused lpss functionsFurquan Shaikh2021-06-071-24/+0
| | | | | | | | | | | | | | | | | This change drops the following unused lpss functions and related code: * soc_lpss_controllers_list * is_dev_lpss These functions were added to determine if a controller is LPSS for performing IRQ configuration. But, these never got used and hence are being dropped. Change-Id: I27bdfbca7c199e823a0e4fdb277e3f22fb6bae7a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/elkhartlake: Update FSP-S storage related configsLean Sheng Tan2021-06-043-2/+68
| | | | | | | | | | | | | | Further add initial Silicon UPD storage settings: - SATA - SD card - eMMC Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Id4145fcf156756a610b8a9a705d4ab99fe7b0bf8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
* soc/intel/elkhartlake: Update FSP-S UPD RP & USB related configsLean Sheng Tan2021-06-042-3/+93
| | | | | | | | | | | | | Further add initial Silicon UPD settings for: - PCIe root ports - USB Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I60afb78a7997b8465dd6318f3abee28f95a65100 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55034 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/elkhartlake: Update FSP-S UPD configs for graphic & chipsetLean Sheng Tan2021-06-041-13/+49
| | | | | | | | | | | | | | | | | | | Further add initial silicon UPD settings for: - graphics & display - chipset lockdown - PAVP - legacy timer - PCH master gating control - HECI This CL also enables HECI 1 in devicetree.cb. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I657f44f8506640c23049614b2db9d1837e6d44ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/54960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
* soc/intel/elkhartlake: Update FSP-S UPD LPSS related configsTan, Lean Sheng2021-06-012-1/+78
| | | | | | | | | | Add Silicon upd settings for LPSS (GSPI/UART/I2C). Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Ib0c3cd1d37ff9892d09d6d86ac50e230549c7e53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* soc/intel/elkhartlake: Update FADT tableTan, Lean Sheng2021-05-301-1/+6
| | | | | | | | | | | | Update FADT table per relevant PM settings: Fix PM Timer block access size and disable C2 and C3 states for the CPU. Further on, set the century byte offset in FADT to point to the common location in CMOS. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I72a57bf8ec61c3eabc4522c2695ae4b16979f188 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54958 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/elkhartlake: Update FSP-M UPD related configsTan, Lean Sheng2021-05-302-20/+137
| | | | | | | | | | | | | | Upload the FSP-M UPD configs. This CL also updated the chip.h and devicetree.cb with the relevant variables and configs. This CL also updated the GPIO related settings (PMC & SD card) in devicetree.cb. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: If6321064b37535b390cf3dd7c41a719c598a0cd7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
* soc/intel/elkhartlake: Minor fix for SCS & XHCI devices in ACPITan, Lean Sheng2021-05-263-8/+5
| | | | | | | | | | | | | 1. Remove the extra UAB devices in xhci.asl 2. Update SD controller ADR in scs.asl 3. Remove the unused SCS PID Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I1906fb4e6893dc5e2b0bc8d85f4a7b2efc85c3a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54867 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/elkhartlake: Update SA & IGD DIDs TableTan, Lean Sheng2021-05-261-13/+17
| | | | | | | | | | | | Update SA & IGD DIDs table as per latest EDS (Doc no: 601458). Add extra SKUs and fix the mismatched SKU numbers accordingly. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I62fd9e6a7cf0fc6f541f3d6d9edd31d41db7279f Reviewed-on: https://review.coreboot.org/c/coreboot/+/54863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
* cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=yArthur Heymans2021-05-181-1/+0
| | | | | | | | | | | This removes the need to include this code separately on each platform. Change-Id: I3d848b1adca4921d7ffa2203348073f0a11d090e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* src: Match array format in function declarations and definitionsPatrick Georgi2021-05-131-1/+1
| | | | | | | | | | | | | | | | gcc 11.1 complains when we're passing a type* into a function that was declared to get a type[], even if the ABI has identical parameter passing for both. To prepare for newer compilers, adapt to this added constraint. Change-Id: I5a1b3824a85a178431177620c4c0d5fddc993b4f Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/elkhartlake: Remove elog.cTan, Lean Sheng2021-04-262-118/+0
| | | | | | | | | | | | | Remove elog.c from EHL soc as EHL does not support chromebook and hence does not need it. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: If66adfe15d00feb0a7fb5e1ced92006a4adebdb7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50173 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-15 23:47:22 +0000