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* soc/intel: Add get_pmbaseEugene Myers2023-06-101-0/+28
| | | | | | | | | | | | | | | | | | | | | | | Originally a part of security/intel/stm. Add get_pmbase to the intel platform setup code. get_pmbase is used by the coreboot STM setup functions to ensure that the pmbase is accessable by the SMI handler during runtime. The pmbase has to be accounted for in the BIOS resource list so that the SMI handler is allowed this access. Original-Change-Id: If6f6295c5eba9eb20e57ab56e7f965c8879e93d2 Original-Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/37990 Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Change-Id: I7f9ef32946a17aa0bbcbc375bc34b48e62620694 Signed-off-by: Eugene Myers <edmyers@tycho.nsa.gov> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* soc/intel/fsp_broadwell_de: Add definition for LGMRJonathan Zhang2021-03-241-0/+1
| | | | | | | | | | Add definition for LPC Generic Memory Range register. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I7c76bacdf692e72849547106f29b614345f505c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51716 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/fsp_broadwell_de: add PCH_DEV_LPC definitionJonathan Zhang2021-03-101-0/+1
| | | | | | | | | Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I2292bf1f6b5d17f95f8e8e41c6d9f07781f22576 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51309 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/fsp_broadwell_de: Check if memory is 'locked'Andrey Petrov2020-06-242-0/+9
| | | | | | | | | | | | | | | | Under certain conditions TXT can "lock" memory controller for security purpose. This manifests itself in IMC's SMbus controller failing all SPD data read requests. FSP does not detect error condition and fails boot with "No memory found" issue. TEST=tested on OCP monolake in 'locked' state Change-Id: If4637e4293421794a89037ff107e87794c40114a Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
* soc/intel: Remove unused codePatrick Rudolph2019-11-041-1/+0
| | | | | | | | | | | | | Delete acpi_create_intel_hpet() which has been replaced by acpi_write_hpet() in the corresponding soc folders some time ago. Change-Id: I788c9ef27cdc575eb8467cbef64ee52f4053e197 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35207 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Guckian Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/broadwell_de: Implement smbios_cpu_get_maximum_freq_mhz()Andrey Petrov2019-10-281-0/+1
| | | | | | | | | | | Determine maximum speed by looking at either turbo flex limit or uncore ratio limit. Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: I0f3a64a40cb1d28d8eb9380c2071ec748e345b88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/36284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* src/soc: change "unsigned" to "unsigned int"Martin Roth2019-10-271-4/+4
| | | | | | | | Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I9c1228d3f9e7a12fe30c48e3b1f143520fed875c Reviewed-on: https://review.coreboot.org/c/coreboot/+/36332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* soc/intel/fsp_broadwell_de: Add function to set DPRPatrick Rudolph2019-10-242-0/+11
| | | | | | | | | | | | | Add code for FSP Broadwell DE to set the DPR. Used by the Intel TXT code. Tested on Intel Broadwell DE using Intel TXT. Change-Id: Ib5e1ba8731e5cea1be9319a1fb9658dba841dc7b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* mainboard/ocp/monolake: Hide IIO root ports before memory initAndrey Petrov2019-10-161-2/+1
| | | | | | | | | | | | | | It turned on some SKUs FSP hangs in Notify stage if IIO root ports are disabled after MemoryInit. To address that hide IIO root ports earlier in romstage. TEST=the patch was ran on affected HW and success was reported Change-Id: I6a2a405f729df14f46bcf34a24e66e8ba9415f9d Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* intel/fsp_broadwell_de: Rename from xx_DEV_FUNCKyösti Mälkki2019-10-061-21/+2
| | | | | | | | | | | | | | Intel adopted xx_DEVFN_xx naming for macros expanding to PCI_DEVFN() starting with apollolake. The ones named xx_DEV_FUNC are being renamed, or dropped, if they were generally not used at all for a platform. Change-Id: I1a8675a4e613a8efc135b05cde36f166acaa7ed4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* intel/pci_devs: Regroup PCI xx_DEVID entriesKyösti Mälkki2019-10-021-21/+23
| | | | | | | | Change-Id: I953e9a7746232b4c40deca55eb6cb3bd7af91496 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/intel/fsp_broadwell_de: move get_busno1() into vtd.cAndrey Petrov2019-09-261-8/+1
| | | | | | | | | | TEST=just build it Change-Id: I34aee507b8c322c816f92cfcae177c069c749ed7 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* soc/fsp_broadwell_de: Add devhide functionalityAndrey Petrov2019-09-242-100/+133
| | | | | | | | | | | | | | Add function to hide IIO PCIe root ports. TEST=On OCP Monolake, hide built-in NIC PCIe root port [0.2.2 and 0.2.3] and make sure OS does not detect built-in NIC. Change-Id: I2fcac5b7d9a7a52a2801c010bfccf247f2a44581 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* soc/fsp_broadwell_de: Move function to get CPUBUSNO(1) into common fileAndrey Petrov2019-09-212-0/+14
| | | | | | | | Change-Id: I189eb8ffce2f0735ad9ba603b1d96786aa00fafb Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* soc/intel: Remove some __PRE_RAM__ useKyösti Mälkki2019-09-131-4/+0
| | | | | | | | Change-Id: I35b44967de4e8d9907dc887fe35407bcaf334adc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35379 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* intel/fsp_broadwell_de: Use smm_subregion()Kyösti Mälkki2019-08-291-16/+2
| | | | | | | | | | | Tested on OCP/Wedge100s: No error is visible in console output, still boots to OS. Change-Id: I986bbe978d3f68693b2d4538ccbcc11cdbd23c6a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34745 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/fsp_broadwell_de: Implement SystemAgent TSEG functionsPatrick Rudolph2019-08-291-0/+3
| | | | | | | | | | | | | | Implement sa_get_tseg_base and sa_get_tseg_size. Used by Intel TXT and the new SMM API. Tested on OCP/Wedge100S. Change-Id: I22123cbf8d65b25a77fbf72ae8411b23b10c13b4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* soc/intel/fsp_broadwell_de: Add ACPI HPET tableJohnny Lin2019-08-271-1/+3
| | | | | | | | | | | | | | | | Tested on Mono Lake TEST=Note the kernel log: hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0 hpet0: 8 comparators, 64-bit 14.318180 MHz counter Change-Id: Idae9a7d3d4233037214d6203996bf44fe5f3a845 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35027 Reviewed-by: Johnny Lin Reviewed-by: Andrey Petrov <anpetrov@fb.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* intel/smm: Define struct ied_header just onceKyösti Mälkki2019-08-151-5/+0
| | | | | | | | Change-Id: I6fc083aa30d05c11c1b6db7b3facacf5ae857c92 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel: Rename some SMM support functionsKyösti Mälkki2019-08-151-20/+0
| | | | | | | | | | | Rename southbridge_smm_X to smm_southbridge_X. Rename most southcluster_smm_X to smm_southbridge_X. Change-Id: I4f6f9207ba32cf51d75b9ca9230e38310a33a311 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34856 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/fsp_broadwell_de: Populate SMBIOS tables with memory informationAndrey Petrov2019-08-142-0/+35
| | | | | | | | | | | | | | | Add code to read SPD data, parse it and save into SMBIOS table. This is implemented for socketed DDR4 chips only. For soldered-down memory this is not implemented and probably won't be ever needed. TEST=tested on OCP Monolake mainboard, and found dmidecode -t memory to work. The stack has also been tested on an out-of-tree board. Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: I1162eb4484dab46f1ab9fe3426eecc4d9378e8e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* soc/fsp_broadwell_de: Implement SMBus read/write over IMCAndrey Petrov2019-08-141-0/+5
| | | | | | | | | | Add read/write functions to hook it up with existing SPD retrieval code. Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: I9f5993dc795badf72751a4e6c9d974119a653e30 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34679 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/fsp_broadwell_de: Enable early integrated UARTAndrey Petrov2019-08-132-0/+65
| | | | | | | | | | | | | | | In order to use internal UART it needs to 'enabled'. This is normally done by FSP. However sometimes internal UART is needed before FSP is invoked. TEST=check if printk() show up in early romstage. Tested on OCP Monolake. Tested on out-of-tree mainboard to see if UART on LPC still works. Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: I88a7b1a38abf9a09137f6dd75a5a9dee104daaca Reviewed-on: https://review.coreboot.org/c/coreboot/+/34683 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/x86: Move smm_lock() prototypeKyösti Mälkki2019-07-131-0/+1
| | | | | | | | | | | | The function implementations are in local platform scopes. Change-Id: I7a3025398b15fe6d2c5a13cdb65f3e62a49c0bc6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34151 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/intel/fsp1_0: Deduplicate codePatrick Rudolph2019-03-161-2/+0
| | | | | | | | | | | | | | | Move ChipsetFspReturnPoint() to drivers/intel/fsp1_0. Allows to have a common entry after FSP-M. Change-Id: I064ae67041c521ee92877cff30c814fce7b08e1f Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31713 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: David Guckian Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
* soc/intel: Standardize names of common MSRsElyes HAOUAS2019-01-071-2/+2
| | | | | | | | | | | | | | | | | | Use defined name in Intel 64 and IA-32 Architectures Software Developer’s Manual. Renamed MSRs are (register address, register name): 0x35 MSR_CORE_THREAD_COUNT 0x121 MSR_EMULATE_PM_TIMER 0x1f4 MSR_PRMRR_PHYS_BASE 0x1f5 MSR_PRMRR_PHYS_MASK 0x2f4 MSR_UNCORE_PRMRR_PHYS_BASE 0x2f5 MSR_UNCORE_PRMRR_PHYS_MASK Change-Id: I53f11a2ce831456d598aa21303a817d18ac89bba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/30288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
* src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS2018-11-121-1/+0
| | | | | | | | Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29300 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* intel: Use CF9 reset (part 1)Patrick Rudolph2018-10-221-24/+0
| | | | | | | | | | | | | Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to perform a "system reset" in their hard_reset() implementation. Replace all duplicate CF9 reset implementations for these platforms. Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* src: Move common IA-32 MSRs to <cpu/x86/msr.h>Elyes HAOUAS2018-10-111-5/+0
| | | | | | | | | | | | | Use "cpu/x86/msr.h" for common IA-32 MSRs and correct IA-32 MSRs names. Change-Id: Ida7f2d608c55796abf9452f190a58802e498302d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28752 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Move compiler.h to commonlibNico Huber2018-10-082-2/+0
| | | | | | | | | | | | | | | Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/intel/fsp_broadwell_de: Fix IA32_MC0_* namesElyes HAOUAS2018-10-011-1/+3
| | | | | | | | | | | | | Regarding the SDMs, IA32_MC0_STATUS register is at 0x401, and IA32_MC0_CTL is at 0x400. So replace MSR at (0x400+1) by IA32_MC0_STATUS and the one at 0x400 by IA32_MC0_CTL. Change-Id: I3f53c80f39078bd0c47c25013657e1169fc6c4a6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* soc/intel/fsp_broadwell_de: Add fixed VT-d MMIO range to the resourcesWerner Zeh2018-09-201-1/+2
| | | | | | | | | | | | | | | | | | | | FSP initializes the VT-d feature on Broadwell-DE and assigns an address space to the MMIO range. coreboot's resource allocator needs to be aware of this fixed resource as otherwise the address can be assigned to a different PCI device. In this case addresses are overlapped and the VT-d range is not accessible any more. To deal with it the right way add a fixed MMIO resource to the resources list if VT-d BAR is enabled. TEST=Booted into Linux and checked coreboot log for resource assignment. Change-Id: I626ac17420eadc0b49031e850f0f40b3b221a098 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/28672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* fsp_broadwell_de: Move DMAR table generation to corresponding VT-d deviceWerner Zeh2018-09-202-4/+5
| | | | | | | | | | | | | | The DMAR table generation depends on the VT-d feature which is implemented in its own PCI device located in PCI:00:05.0 for Broadwell-DE. Add a new PCI driver for this device and move DMAR table generation to this device driver. Change-Id: I103257c73f5e745e996a441a2535b885270bc204 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/28671 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* soc/intel/fsp_broadwell_de: Get rid of device_tElyes HAOUAS2018-06-041-2/+2
| | | | | | | | | | Use of device_t has been abandoned in ramstage. Change-Id: I68c455d4bc524c2dd2d3ba87ab6641e70c78521c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26589 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* soc/fsp_broadwell_de: Add support for GPIO handlingWerner Zeh2017-10-193-0/+138
| | | | | | | | | | | Add functionality to initialize, set and read back GPIOs on FSP based Broadwell-DE implementation. Change-Id: Ibbd86e2142bbf5772eb4a91ebb9166c31d52476e Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/22034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* intel/fsp_broadwell_de: Add timestamp functionalityWerner Zeh2017-10-121-0/+3
| | | | | | | | | | | | Add a little code to enable timestamps on FSP based implementation of Broadwell-DE. I have tested it by reading back the timestamps with cbmem utility once the board has booted into Lubuntu. Change-Id: Idaa65a22a00382bf0c37acf2f5a1e07c6b1b42d9 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/21932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Rename __attribute__((packed)) --> __packedStefan Reinauer2017-07-131-1/+2
| | | | | | | | | | | Also unify __attribute__ ((..)) to __attribute__((..)) and handle ((__packed__)) like ((packed)) Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/15921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* fsp_broadwell_de: Switch CPU to high frequency modeWerner Zeh2017-05-051-0/+2
| | | | | | | | | | | | | | | | | According to Yang York the FSP is responsible for switching the CPU into high frequency mode (HFM). For an unknown reason this is not done for the BSP on my platform though the APs are switched properly. This code switches the CPU into HFM which makes sure that all cores are in high frequency mode before payload is started. It should not harm the operation even if FSP was successful in switching to HFM. Change-Id: I91baf538511747d1692a8b6b359df5c3a8d56848 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/19537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* fsp_broadwell_de: Add SMM codeWerner Zeh2017-04-285-7/+143
| | | | | | | | | | | | | | | | Add basic SMM support for Broadwell-DE SoC. The code is mainly based on the SMM implementation of Broadwell with a few differences: - EMRR is now called PRMRR and the UNCORE part of it is not available - SMM_FEATURE_CONTROL is no longer a MSR but is now located in PCI space - currently only SERIRQ-SMI has a handler Change-Id: I461a14d411aedefdb0cb54ae43b91103a80a4f6a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/19145 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* intel: Fix copy/paste error in license textMarshall Dawson2017-01-161-1/+1
| | | | | | | | | | | Change all instances of "wacbmem_entryanty" to "warranty". Change-Id: I113333a85d40a820bd8745efe917181ded2b98bf Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/18136 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* fsp_broadwell_de: Add Kconfig switch for SERIRQ operation modeWerner Zeh2016-09-131-0/+4
| | | | | | | | | | | | | The serial IRQ (SERIRQ) used by the LPC interface can operate either in continuous or in quiet mode. Add a Kconfig switch to select the desired mode. This switch can now be used on mainboard level to enable the needed mode per mainboard. Change-Id: Ibe246b88164a622f9c71ebe7bab752a083a49a62 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/16575 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
* siemens/mc_bdx1: Enable decoding for COM 3 & COM 4 on LPCWerner Zeh2016-09-121-0/+4
| | | | | | | | | | | | Since this mainboard provides 4 COM ports on LPC, enable decoding of the corresponding addresses using the generic LPC decode registers. Change-Id: I0e93d40dca01d55f3567a18c7ec02269e3bec466 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/16535 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* fsp_broadwell_de: Add DMAR table to ACPIWerner Zeh2016-08-033-0/+12
| | | | | | | | | | | | | | Create DMAR table for Broadwell-DE SoC. TEST=Booted MC BDX1 into lubuntu15, dumped ACPI tables with acpidump and disassembled DMAR table using iasl. The table contents are as expected and the kernel loads DMAR table without errors. Change-Id: I7933ba4f5f0539a50f2ab9a5571e502c84873ec6 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15913 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
* soc/intel/fsp_broadwell_de: use common Intel ACPI hardware definitionsAaron Durbin2016-07-151-8/+2
| | | | | | | | | | | | | | Transition to using the common Intel ACPI hardware definitions generic ACPI definitions. BUG=chrome-os-partner:54977 Change-Id: Iecd94494cb568b20bdf6649b46a9a9586074bdc7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15672 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: York Yang <york.yang@intel.com>
* fsp_broadwell_de: Add SMBus driver for ramstageWerner Zeh2016-07-142-0/+53
| | | | | | | | | | | | | There is currently a SMBus driver implemented for soc/intel/broadwell which nearly matches Broadwell-DE as well. Use this driver as template and add minor modifications to make it work for Broadwell-DE. Support in romstage is not available and can be added with a different patch. Change-Id: I64649ceaa298994ee36018f5b2b0f5d49cf7ffd0 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15617 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* intel/fsp_broadwell_de: Do not use hard coded SCI IRQ for ACPIWerner Zeh2016-07-071-0/+10
| | | | | | | | | | | | | | | The SCI interrupt can be routed to different IRQs using ACPI control register. Instead of using hard coded IRQ9 for ACPI table generation read back the register and return the used IRQ number. This way SCI IRQ can be modified (e.g. for a given mainboard) and ACPI tables will remain consistent. Change-Id: I534fc69eb1df28cd8d733d1ac6b2081d2dcf7511 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15548 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: York Yang <york.yang@intel.com>
* PCI: Use PCI_DEVFN macro instead of DEV_FUNCWerner Zeh2016-07-061-18/+20
| | | | | | | | | | | | | | | | There are several different macros available to convert a PCI device and function to a single 8 bit value. One is PCI_DEVFN and is defined in device/pci_def.h. The other is DEV_FUNC and is defined in several intel fsp based chipset implementations. In fsp_broadwell_de DEV_FUNC is even used without being defined at all. This patch unifies the situation so that only PCI_DEVFN is used. Change-Id: Ia1c6d7f3683badc66d15053846936d88aa836632 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15546 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* fsp_broadwell_de: Enable Super I/O address range decodeWerner Zeh2016-06-301-1/+3
| | | | | | | | | | | | | | | | | If there is an external 16550 like UART, one needs to enable the appropriate address ranges before console_init() is called so that the init sequence can reach the external UART. Otherwise the UART will only start working in ramstage and will produce unreadable characters in romstage due to the lack of initialization. Tested-on: Siemens MC_BDX1 Change-Id: Iafc5b5b6df14916c5ed778928521d4a8f539cf46 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15495 Tested-by: build bot (Jenkins) Reviewed-by: York Yang <york.yang@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* soc/intel: Add Broadwell-DE SoC supportYork Yang2016-04-1411-0/+566
Initial files to support Broadwell-DE SoC. This is FSP 1.0 based project and is based on Broadwell-DE Gold release. Change has been verified on Intel Camelback Mountain CRB. Change-Id: I20ce8ee8dd1113a7a20a96910292697421f1ca57 Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: https://review.coreboot.org/14014 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-23 19:33:11 +0000