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* soc/intel/tigerlake: Add SPI_DMI_DESTINATION_ID for PCH-HJeremy Soller2021-08-241-0/+4
* soc/intel/tigerlake: Set UserBd to recommended default for PCH-HJeremy Soller2021-08-241-1/+4
* soc/intel/tgl: Add PCR_PSF3_T0_SHDW_PMC_REG_BASE for PCH-HJeremy Soller2021-08-241-0/+4
* soc/intel/tigerlake: Add TGL-H PEG portsJeremy Soller2021-08-244-1/+39
* soc/intel/tigerlake: Add PCIe root ports for PCH-HJeremy Soller2021-08-243-5/+207
* soc/intel/tigerlake: Add PCH-H GPIO definitionsJeremy Soller2021-08-2410-8/+1110
* soc/intel/tigerlake: Add PCH-H PMC GPE group definitionsJeremy Soller2021-08-241-0/+17
* soc/intel/tigerlake: Add PCH-H chipset devicetreeJeremy Soller2021-08-242-0/+196
* soc/intel/tigerlake: Add TGL-H power limitsJeremy Soller2021-08-242-5/+15
* soc/intel: Add TGL-H CPUIDJeremy Soller2021-08-241-0/+1
* soc/intel/common: Add TGL-H PCI IDsJeremy Soller2021-08-191-0/+13
* mb/*/{tglrvp,volteer,deltaur}: move cpu_cluster configuration to chipset.cbMAULIK V VAGHELA2021-08-161-0/+2
* soc/intel/tigerlake: Select SF_MASK_2WAYS_PER_BIT if eNEM is enableSubrata Banik2021-08-151-0/+1
* soc/intel/tgl: Hook up ucode for TGL-U and TGL-RTim Crawford2021-08-132-1/+3
* soc/intel/tigerlake: Clean up FSP chipset lockdown configurationFelix Singer2021-08-121-11/+5
* soc/intel/tgl: Allow setting PCIe subsystem IDs after FSP-STim Crawford2021-08-121-0/+58
* Move post_codes.h to commonlib/console/Ricardo Quesada2021-08-042-5/+5
* soc/intel/*: Allow configuring 8254 timer via CMOSSean Rhodes2021-08-031-2/+5
* src/*: Specify type of `CBFS_SIZE` onceAngel Pons2021-07-261-1/+0
* soc/intel/common: Rename kconfig PMC_EPOCLean Sheng Tan2021-07-191-1/+1
* soc/intel/tigerlake: Make use of `cpu/intel/cpu_ids.h'Subrata Banik2021-07-173-3/+3
* soc/intel/tigerlake: Use `is_devfn_enabled()` for Crashlog UPDsSubrata Banik2021-07-151-4/+2
* src: Introduce `ARCH_ALL_STAGES_X86`Angel Pons2021-07-021-1/+0
* soc/intel: Refactor `xdci_can_enable()` functionAngel Pons2021-07-011-4/+1
* soc/intel/tigerlake: Send End-of-Post message to CSETim Wawrzynczak2021-06-302-6/+7
* soc/intel/common: Move PMC EPOC related code to Intel common codeLean Sheng Tan2021-06-304-32/+1
* src: Move `select ARCH_X86` to platformsAngel Pons2021-06-301-0/+1
* soc/intel/tigerlake: Enable support for common IRQ blockTim Wawrzynczak2021-06-297-168/+224
* soc/intel: Drop casts around `soc_read_pmc_base()`Angel Pons2021-06-281-2/+1
* soc/intel/tigerlake: Use devfn_disable() function for XDCISubrata Banik2021-06-231-8/+3
* soc/intel/{alderlake,tigerlake}: Fix typo in pmc.hWerner Zeh2021-06-171-1/+1
* soc/intel/tigerlake: Make use of is_devfn_enabled() functionSubrata Banik2021-06-163-53/+22
* util: Add DDR4 generic SPD for MT40A512M16TB-062E:RWisley Chen2021-06-141-0/+2
* soc/intel/tigerlake: Move MAX_CPUS to KconfigAndy Pont2021-06-101-0/+4
* soc/intel/tigerlake: Hook up FSP repositoryFelix Singer2021-06-103-37/+52
* cpu/x86: Default to PARALLEL_MP selectedKyösti Mälkki2021-06-071-1/+0
* soc/intel: Drop unused lpss functionsFurquan Shaikh2021-06-071-23/+0
* soc/intel/tigerlake: Return TBT PowerResource from PR0 and PR3John Zhao2021-05-272-14/+20
* soc/intel/tigerlake: Add validity for TBT firmware authenticationJohn Zhao2021-05-261-0/+4
* cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=yArthur Heymans2021-05-181-1/+0
* soc/intel/tigerlake: Allow devicetree to fill UPD related to TCSS OCNick Vaccaro2021-05-143-0/+23
* src: Match array format in function declarations and definitionsPatrick Georgi2021-05-131-1/+1
* soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXITKane Chen2021-05-072-2/+13
* soc/intel/{adl,tgl,jsl}: Add smihandler_soc_disable_busmasterKane Chen2021-05-071-0/+8
* soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias padsTim Wawrzynczak2021-05-064-15/+29
* soc/intel/tigkerlake: Add IOM PCR PIDTim Wawrzynczak2021-05-061-0/+1
* soc/intel/tigerlake: Add known CPU Port IDs for GPIO communitiesTim Wawrzynczak2021-05-062-0/+10
* soc/intel/tigerlake: Add known GPIO virtual wire informationTim Wawrzynczak2021-05-061-0/+27
* soc/intel/*: Update data types for variables holding PCH_DEVFN_* macrosTim Wawrzynczak2021-05-031-1/+1
* device: Switch pci_dev_is_wake_source to take pci_devfn_tTim Wawrzynczak2021-05-031-21/+8
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