| Commit message (Collapse) | Author | Age | Files | Lines |
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Add ADL-S specific table with IRQ constraints to avoid accessing
non-existent devices.
Also when using debug FSP, silicon init would assert on assigning IRQs
for non-existent devices. This patch fixes the problem.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ib4464a85bc11a8603bf471ea348bbfc9481db4aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Due to incorrectly interpreted DOC #630603, the reserved range
remains the same for all ADL platforms and is sync with
src/soc/intel/common/block/acpi/acpi/northbridge.asl which defines the
range as 0xfc800000-0xfe7fffff. The range 0xfe000000-0xfe7fffff was
only mean for static allocations, but the rest is also reserved. The
only difference between ADL-S and other ADL platforms is Trace Hub
base.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I9b1f79cc351de422acf182c27870c29dbe57fe4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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The `limit` field for the PMC fixed BAR was incorrectly set to the `base
+ size + 1`, where it should be `base + size - 1`, to correctly tell the
allocator the limit.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Icf51333f438ce2597c008b48305cf5816dacd3f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65461
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The `limit` field for the PMC fixed BAR was incorrectly set to the `base
+ size + 1`, where it should be `base + size - 1`, to correctly tell the
allocator the limit.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib2d8c7ffe87fdd970f3172bb4e6b2c9386859ab3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65460
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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List of changes:
1. Select common ACPI Kconfig to include common ACPI code block
from IA-common code
2. Select ACPI Kconfig support for wake up from sleep states.
3. Add SoC ASL code in ASL 2.0 syntax for SoC IPs like IPU, ISH,
LAN, HDA etc.
BUG=b:224325352
TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'.
Change-Id: Iebe3d38f50e202d75add88f336b5f3e9ba9f5a22
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64168
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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List of changes:
1. Add required SoC programming till ramstage
2. Include only required headers into include/soc
3. Fill required FSP-S UPD to call FSP-S API
BUG=b:224325352
TEST= Build 'util/abuild/abuild -p none -t google/rex -a -c max'.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: Ie746c0bfcf1f315a4ab6f540cc7c4933157551d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63364
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Default VBOOT_HASH_BLOCK_SIZE is 1 KiB and increasing it to 4 KiB
helps in improving overall boot time since it reduces hashing and
body loading time (~30ms).
Backport changes from commit hash 84532dae1 (soc/intel/alderlake:
Change VBOOT_HASH_BLOCK_SIZE to 4 KiB).
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3784b99bf06e0c03d123f290a98a0b1e4528b8d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64792
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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List of changes:
1. Add required SoC programming till romstage
2. Include only required headers into include/soc
3. Fill required FSP-M UPD to call FSP-M API
BUG=b:224325352
TEST=Build 'util/abuild/abuild -p none -t google/rex -a -c max'.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I3d5c6ceb7f97429ff903e7577186e8d8843c1f14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63363
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add Raptor Lake specific CPU, System Agent, PCH, IGD device IDs.
References:
RaptorLake External Design Specification Volume 1 (640555)
600/700 Series PCH External Design Specification Volume 1 (626817)
BUG=b:229134437
BRANCH=firmware-brya-14505.B
TEST=Booted to OS on adlrvp + rpl silicon
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Change-Id: I8e8b9ec6ae82de7d7aa2302097fc66f47b782323
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65117
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ic2b9a22bc6c32030f960d59b2874be5459c3ba28
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Code taken from TGL base.
TEST=Boot MSI PRO Z690-A WIFI DDR4 and see all devices have SSID
applied
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I3a6d299ec40bac8e29d06926572e375d7d835e29
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Extend the code to support ADL-S PCIe Root Ports.
Based on DOC #619362 and #619501.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ibb57ad5b11684c0079e384d9a6ba5c10905c1a23
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63654
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add PCIe Root Ports, USB ports and SIO devices for ADL-S chipset.
Add IRQ routing tables for PCIe Root ports up to 28th.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I508fa1396b07f38801bcf50cdfdc876356d7ae9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63785
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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clcok ---> clock
Change-Id: Ie41524f6500479162984fa9050d942f4e295f00a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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The details about how the CPU multiprocessor init (MP) has migrated
from coreboot to FSP can be found in
https://doc.coreboot.org/soc/intel/mp_init/mp_init.html.
The major reason behind this migration is to support the Intel
proprietary and restricted CPU feature programming which can't be
performed if coreboot sets the BIOS_DONE or BIOS Reset CPL as part
of coreboot MP Init flow (prior to calling FSP-S). Hence, the new
flow introduced with Tiger Lake platform forced having monolithic
MP Init peformed by FSP (using coreboot MP PPI wrapper code).
The last 3-4 years of FSP doing MP Init has demonstrated ample
issues during platform bringup which is specific to UEFI MP Service
implementation and not relevant to open source coreboot. This new
flow makes the debug and validation aspect complicated where
any FSP MP Init code changes should have been validated with coreboot
MP PPI wrapper else might cause some failure, unfortunately,
the validation commitment has never been met, hence, issue debugging
is the only solution that remains in practice.
Most importantly, the restricted feature programming which demanded
closed source MP Init (for features like SGX and C6DRAM) has never
been enabled in coreboot (starting with Alder Lake, the SGX feature
has been dropped).
This patch attempts to decouple FSP-S doing MP Init from the rest
of the FSP-S silicon init and introduces 2nd MultiPhase SI init
which allows bootloader to perform the mandatory SoC programming
before FSP-S has done with PM programming (a.k.a set the reset CPL).
The core/uncore BWG suggests the minimum SoC programming before
BIOS Reset CPL is set. coreboot uses the MultiPhaseSI Init Index 2
to perform the required CPU programming before enabling the BIOS
Reset CPL.
This implementation would allow us to get rid of FSP running CPU
feature programming and additionally make several EDK2 MP service
modules optional (those are packed to create FSP-S blob).
In summary, this change would allow coreboot to utilize open source
MP init without running into FSP-S related code blocks.
Note: At present, Intel Alder Lake FSP doesn't have support for
MultiPhase SI Init, Index 2 (submitted a FSP code changes over
chrome-internal to enable this feature to decouple MP Init from
FSP-S init).
BUG=b:233199592
TEST=Build and boot google/taeko to ChromeOS.
Perform several thousands cycles of suspend test and power cycle
without running into any issue.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I314c63c917ef6fdd32f364b2c60bae22486b8b74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64979
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Introduce three functions:
- new_padbased_table:
Returns the gpio pad number based table
- gpio_padbased_override:
Must pass the table with padbased table
- gpio_configure_pads_with_padbased:
Must pass the table with padbased table, will skip configures the
unmapped pins by check pad and DW0 are 0.
Some boards may have complex, SKU-based GPIO programming. This
patch provides for a simpler pattern of controlling overrides of
GPIO programming by providing a table of pad configuration indexed
by pad number. Thus, pad state can be overwritten over multiple
overrides until the final takes place, and then all GPIO
programming is performed at once.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I8b99127b73701b50a7f2e051dee9d12c9da9b741
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64712
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ia44be7d63b0e6e16a49695d430715a7e5785d530
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55925
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace xx_resource() calls with calls that take the base
and size arguments as-is, without dividing by KiB (or >> 10).
With replacement of the allocator/constructor function
caller can use log_resource() instead.
Change-Id: I7e4e1e5a779c418f369dd2dab8c811f67ad1399f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55477
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch drops FSP Debug interface selection as coreboot now decides
the UART inerface to redirect the debug msg.
BUG=none
TEST=Able to see all coreboot and FSP debug log with and without this
patch.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: If8c07d7e63c5d445fdb77ac38b99217bf015e15f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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These changes made my crude pattern matching work with
coccinelle simpler.
Change-Id: I83f3ef38b8663640594b4d726838f7a6f96a58a2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Move the Intel top_swap feature into the intel/common Kconfig file.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I3ed649aaeb51c2250be9473114c17d3f191d2c38
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Most of the src/soc/Kconfig files are only there for AMD and Intel to
load the main SoC Kconfig files before any common files. That can be
done in src/Kconfig instead. Moving the loads to the lower level allows
the removal of all but the Intel soc/Kconfig file, which can be removed
in a follow-on patch.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I5061191fe23e0b7c745e90874bd7b390806bbcfa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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This CL fixes my previous CL (commit ca741055e)
which introduced a couple of issues found by Coverity (see below).
The Coverity explanation is: "Potentially overflowing expression "size_field * 1048576U" with type "unsigned int" (32 bits, unsigned) is evaluated using 32-bit arithmetic, and then used in a context that expects an expression of type "uint64_t" (64 bits, unsigned)."
*** CID 1490122: Integer handling issues (OVERFLOW_BEFORE_WIDEN)
/src/soc/intel/alderlake/systemagent.c: 305 in get_dpr_size()
*** CID 1490121: Integer handling issues (OVERFLOW_BEFORE_WIDEN)
/src/soc/intel/alderlake/systemagent.c: 254 in get_dsm_size()
BUG=b:149830546
BRANCH=firmware-brya-14505.B
TEST='emerge-brya coreboot chromeos-bootimage' builds correctly.
Tested on an Anahera device which successfully boots to ChromeOS
with kernel version 5.10.109-15688-g857e654d1705.
Change-Id: Ib2d66ad24a5ad67b51036ad376a6938f698134c3
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65212
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the desktop board types as per DOC #573387.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I8cca98f0fac51e537b472958ee602e116b48f6d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
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This patch fixes an issue introduced with commit ca741055e
(soc/intel/adl: Add missing claimed memory regions) where PRMRR base
should be read using MSR 0x2a0 and mask from MSR 0x1f5 instead
System Agent PCI configuration space.
With this change, coreboot is able to read PRMRR base when the
PRMRR size > 0.
TEST=Able to read PRMRR base MSR 0x2a0 in proper with this CL.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3770b1a92dbd2552cf1b9764522c9cac9f29c13c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Eran Mitrani <mitrani@google.com>
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Enable PwrOptEnable FSP S UPD and hook it to the inverted value of
SataPwrOptimizeDisable to allow it to be disabled from the devicetree.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I056fd7b16dadb213b3326523b0c7943ce35b8dc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9b64375d905d93a8db726202ed2ce932fa536da3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add GPIO definitions for ADL-S, similarly to how TGL/TGL-H handles
the split.
Based on:
- Intel PCH-S EDS Vol2 (#621483)
- Alderlake-S FSP
- slimbootloader sources
- Linux alderlake-pinctrl driver
Change-Id: I0fd1dc645c19c33bf14424703f966271e884ed3d
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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MAX_PCIE_CLOCK_SRC is not an user-configurable option.
Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: Ia49f6e236e8853c377e9096500d96f21dbdc9b8d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65298
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add Meteor Lake SA device ID 0x7d14 (4+8, 15W).
BUG=b:224325352
TEST=Able to build MTL SoC and verified SA DID is now shown proper.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I051a40136ed89e837945bf4569c77d2a80375ed6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65111
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The file is already present in the microcode submodule repository.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ib284908db165dc95a5895979174512818f2aceff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65292
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch ensures all APs finish the task and continue
before_post_cpus_init() if coreboot decides to perform multiprocessor
initialization using native coreboot drivers instead of using
FSP MP PPI implementation.
BUG=b:233199592
TEST=Build and boot google/kano to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3b76974ab19323201bf1dca9af423481a40f65c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65173
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch creates choice that lists all possible options to perform
MP Init as below:
1. USE_FSP_MP_INIT: Allow coreboot to bring APs from reset and FSP
runs feature programming based and selects MP_SERVICES_PPI_V2 config.
2. USE_COREBOOT_MP_INIT: Allow coreboot to perform MP Init (both AP
init and feature programming) using native implementation.
Additionally, selects required RELOAD_MICROCODE_PATCH when coreboot
is expected to run MP Init.
Refactor SoC code to allow required FSP UPD override based on
selected MP Init option.
BUG=b:233199592
TEST=Build and boot google/taeko to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I20adc1935890c4c6bcd11fd086838f15d0723932
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64977
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch ensures to perform core PRMRR sync if SoC decides to
perform MP Init using coreboot native implementation.
Also, implement a function to allow calling `init_core_prmrr()`
for all CPUs from `before_post_cpus_init()`.
BUG=b:233199592
TEST=Build and boot google/kano to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I9b6222c98ff278419fa8411054c0954689e1271e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64978
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch calls into `intel_reload_microcode() function to load
second microcode patch after BIOS Done bit is set and before
setting the BIOS Reset CPL bit.
Also, remove redundant microcode reloading debug print.
BUG=b:233199592
TEST=Build and boot google/kano to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Icb3fcfd7ef5478be0a40f8f1358f55c0247b4914
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65157
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There is a lot of going back-and-forth with the KiB arguments, start
the work to migrate away from this.
Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Let's not rely on the type to get the correct result,
casting 0 to 0ull made the result wrong.
Change-Id: I6dfba3800170fdd4267e3bb74c55b05533c101fc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Hook Up SataPortsEnable to the devicetree. As the default value is 0,
set both [0] and [1] in all mainboards so they aren't affected.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ica8cf9484a6e6fe4362eabb8a9a59fcaf97c1bd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64524
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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ADL-S has more USB ports than mobile chipsets. Add missing ACPI
names.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ice5f7784f9de0364681be00fc5cc445caf9d1b3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63655
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Hook up C1e FSP S UPD which enables enhanced C-states, to
enhanced_cstates. This allows it to be enabled in the
devicetree with a value of "1" as the default is disabled.
C1e exists on both APL and GLK, and has been there since their
initial releases.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie803a75ac9fb64a6c21b31baeea7b736e4fbf5fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Hook up FSP S UfsEnabled UPD (1d.0) to devicetree.
UFS only exist on GLK, and has been there since its
initial releases.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1976bfd340c728c64aaf36d296ac41dcd47bfc61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Allow configuring the LPC IO registers in the devicetree with:
* gen1_dec
* gen2_dec
* gen3_dec
* gen4_dec
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I2a7ab3faf927cda76640227feff4e19017442897
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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When an enabled root port without pcie_rp clock being specified, the
empty structure provides invalid info, which indicates '0' is the
clock source and request. If a root port does not use clock source, it
should still need to provide pcie_rp clock structure with flags set to
PCIE_RP_CLK_SRC_UNUSED. If flags, clk_src, and clk_req are all '0', it
is considered that pcie_rp clock structure is not provided for that
root port.
Add check and skip for enabled root port that does not have clock
structure. In addition, a root port can not use a free running clock or
clock set to LAN.
Note that ClockUsage is either free running clock, LAN clock, or the
root port number which consumes the clock.
BRANCH=firmware-brya-14505.B
Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: I17d52374c84ec0abf888efa0fa2077a6eaf70f6c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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The patch renames identifiers (macros, function and structure names) in
the basecode/debug/debug_feature.c to generic names so that they can be
used to control the features which may have to be controlled either
during pre and post memory.
Currently, the naming of identifiers indicate that it meant to control
the features which can be controlled during only pre-memory phase.
TEST=Build code for Gimble
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I53ceb25454027ab8a5c59400402beb6cc42884c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Use Intel common SoC msr.h for Denverton refactor
Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
Change-Id: Ic5f99fbcd2f936d4e020bd9b74b65dcd6e462bdc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61016
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Use Intel common SoC SPI code for Denverton refactor
Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
Change-Id: Ic1d57c6b348adb934785b0e2bec4e856f0bf8d77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61014
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Define total GPIO pins as TOTAL_PADS.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I220b6f1a968667a68c30c7287ab5af1912959e3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Define total GPIO pins as TOTAL_PADS.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ic7c48415d1fa3067ac62520a542058e7cab45941
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
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Define total GPIO pins as TOTAL_PADS.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I40294339c79f5db1850ccd546292c67169890b2c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65161
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Based on DOC #619501, #619362 and #618427
TEST=Boot MSI PRO Z690-A DDR4 WIFI and see the silicon info is
reported as ADL-S.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I8051113515ef63fc4687f53d25140a3f55aadb6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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