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* soc/intel/skylake: Make use of Intel SPI common blockSubrata Banik2017-11-113-52/+3
| | | | | | | | | | | TEST=Build and boot soraka/eve Signed-off-by: Subrata Banik <subrata.banik@intel.com> Change-Id: I10de3ff75a3b063c4c46471e380bbbe2630c35f3 Reviewed-on: https://review.coreboot.org/22361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/intel/{cannonlake,skylake}: Add _soc_ prefix in spi soc routineSubrata Banik2017-11-116-46/+64
| | | | | | | | | | | This ensures that function callback into the SoC code. Change-Id: Idc16d315ba25d17a2ab537fcdf0c2b51c8802a67 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/intel/common/block: Add Intel common SPI supportSubrata Banik2017-11-114-0/+130
| | | | | | | | | | | | SOC need to select specific macros need to compile common SPI code. Change-Id: I82f7d1852d12ca37f386b64a613a676753da959c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/intel/cannonlake: Remove structure variable initialization with 0Subrata Banik2017-11-101-3/+0
| | | | | | | | | | | | Variable without an initializer will default to 0 hence no need of an explicit initialization. Change-Id: I208d5e475600b102cd3d972919b170c10c790b32 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* soc/intel/common: Fix CSE common code to accomodate Skylake/KabylakeSubrata Banik2017-11-101-3/+22
| | | | | | | | | | | | | | This patch ensures Skylake/Kabylake soc can make use of common CSE code in order to perform global reset using HECI interface. TEST=Build and boot on soraka/eve/reef/cnl-rvp Change-Id: I49b89be8106a19cde1eb9b488ac660637537ad71 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* soc/intel/apollolake: Include HECI BAR0 address inside iomap.hSubrata Banik2017-11-101-0/+2
| | | | | | | | | | | | | | This ensures HECI1_BASE_ADDRESS macro is coming from respective SoC dirctory and not hardcoded inside common cse code. As per firmware specification HECI1_BASE_ADDRESS might be different between different socs. Change-Id: I502b5b41b449bb07f14f07435bf311bbd4f943b6 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* soc/intel/kabylake: Add Dialog da7219 NHLT blob supportNaveen Manohar2017-11-074-0/+87
| | | | | | | | | | | | | | | | | | | | Add APIs and required parameters for creating Dialog da7219 SSP endpoints in NHLT table. The use of a NHLT table is required to make audio work on the kabylake SoCs employing the internal DSP. The table describes the audio endpoints (render vs capture) along with their supported formats. BUG=b:68686020 TEST=check that NHLT table for da7219 is created properly Change-Id: I57b88873f1c59c8aadf8eec3c80a9d95165a2cc3 Signed-off-by: Naveen Manohar <naveen.m@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/22324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* src: Fix all Siemens copyrightsMario Scheithauer2017-11-075-5/+5
| | | | | | | | | | | | Some Siemens copyright entries incorrectly contain a dot at the end of the line. This is fixed with this patch. Change-Id: I8d98f9a7caad65f7d14c3c2a0de67cb636340116 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/22355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* soc/intel/denverton_ns: re-factor HSIO configurationJulien Viard de Galbert2017-11-074-27/+14
| | | | | | | | | | | | The main goal is to allow configuring the HSIO lines from the mainboard code. Also share the code for both romstage and ramstage. Remove explicit dependency on the harcuvar mainboard. Change-Id: Iec65472207309eae878d14eef5bc644b80fdbb1d Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/22309 Reviewed-by: FEI WANG <wangfei.jimei@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cannonlake: Add DSP supportLijian Zhao2017-11-041-0/+1
| | | | | | | | | | | | | | Add dsp driver support for cannonalake, especially the scan_bus function of Audio controller required. TEST=N/A Change-Id: I573fecedbd4d6619112765c3f2f8baccabeb5ac5 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
* soc/intel/cannonlake: Install common i2cLijian Zhao2017-11-044-0/+92
| | | | | | | | | | | | Add common i2c support for cannonlake. TEST=N/A Change-Id: I5c60b0579f9e6050308896dcb13dda0bbb724d2b Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22238 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/apollolake: Fix nhlt blobs path for GLKHannah Williams2017-11-041-0/+4
| | | | | | | | | | | Change-Id: Iabea32654918575c952857145ee6edb165899baf Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/22277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
* sb and soc: Enforce correct offset of member "chromeos" in global_nvs_tJonathan Neuschäfer2017-11-046-8/+20
| | | | | | | | | | | | | | The padding has recently been broken in commit 90ebf96df5 ("soc/intel/skylake: Add GNVS variables and include SGX ASL") and fixed again in commit af88398887 ("soc/intel/skylake: Fix broken GNVS offset for chromeos"). Avoid this bug in the future. Change-Id: I1bf3027bba239c8747ad26a3130a7e047d3b8c94 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* soc/intel/skylake: Update coding style for i2cLijian Zhao2017-11-041-12/+24
| | | | | | | | | | | | | | From comment from https://review.coreboot.org/#/c/22238/, the coding style need to be update. TEST=N/A Change-Id: Id022648951c0f11216aa32f422b5095476f82f8c Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* soc/intel/apollolake: Move to common dsp driverLijian Zhao2017-11-043-38/+1
| | | | | | | | | | | | Move dsp driver implementation to common dsp driver. TEST=Boot up and check dsp driver loaded or not in OS. Change-Id: Ia2be1c9f18e0e110600bd56a0b6cb8d40ca5e01f Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/intel/common: Add common dsp driverLijian Zhao2017-11-043-0/+44
| | | | | | | | | | | | | Audio DSP pci driver can be common across different platforms. TEST=N/A. Change-Id: Ia9206657864b8795799dc71af54996017c1eec57 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22232 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
* soc/intel/quark/spi: Correct conversion specifierPaul Menzel2017-11-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Use the correct conversion specifier for `size_t` to fix the error below. ``` from src/soc/intel/quark/spi.c:18: src/soc/intel/quark/spi.c: In function 'xfer': src/soc/intel/quark/spi.c:107:20: error: format '%ld' expects argument \ of type 'long int', but argument 3 has type 'unsigned int' \ [-Werror=format=] printk(BIOS_ERR, "bytesin > %ld\n", sizeof(ctrlr->data)); ^ ``` Found-by: gcc (Debian 7.2.0-8) 7.2.0 Change-Id: I3974d116e85715086a2bd5533a80a20c4cc43303 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/22130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
* soc/intel/common/block/lpc: Make integer literal unsigned longPaul Menzel2017-11-031-1/+1
| | | | | | | | | | | | | | | ``` CC romstage/soc/intel/common/block/*/lpc_lib.o src/soc/intel/common/block/lpc/lpc_lib.c:91:17: warning: The result of the '<<' expression is undefined alignment = 1 << (log2_ceil(window_size)); ~~^~~~~~~~~~~~~~~~~~~~~~~~~~~ ``` Change-Id: I9bf2283e23ca7739a7e5b0993d9b6034ea28fb78 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/22201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* soc/intel/common/block: Make integer literal unsigned longPaul Menzel2017-11-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | Fix the warning below by making the integer literal unsigned. ``` CC bootblock/soc/intel/common/block/*/lpc_lib.o src/soc/intel/common/block/lpc/lpc_lib.c:91:17: warning: The result of the \ '<<' expression is undefined alignment = 1 << (log2_ceil(window_size)); ~~^~~~~~~~~~~~~~~~~~~~~~~~~~~ ``` Found-by: Clang static analyzer scan-build (clang version 4.0.1-6 (tags/RELEASE_401/final)) Fixes: e237f8b7 (soc/apollolake/lpc: Open I/O to LPC based on resource allocation) Change-Id: I094fb469f020f3c1fae936e304b4458858842a8e Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/22198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* soc/intel/apollolake: Add APL CPU device IDMario Scheithauer2017-11-034-5/+3
| | | | | | | | | | Add Apollo Lake CPU device ID for E0 stepping. Change-Id: I28fa222cd28b783d22c347cdbbd769e66bf10c30 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/22149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/intel/apollolake: Set CPU to Max Non-Turbo RatioMario Scheithauer2017-11-031-0/+7
| | | | | | | | | | | | | | | If the Running Average Power Limits (RAPL) feature is disabled, the CPU should be set to the Max Non-Turbo Ratio. RAPL is switched off by CONFIG_APL_SKIP_SET_POWER_LIMITS. Furthermore, a frequency change should be prevented by disabling Enhanced Intel Speedstep Technology (EIST). So the CPU should run with constant frequency with this setting. Change-Id: I67020f7e75700255629294fd9bcf67ee01765a01 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/22148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/intel/cannonlake: Use SCS common codeBora Guvendik2017-11-014-0/+44
| | | | | | | | | | This patch uses common SCS library to set up sd card. Change-Id: I7978bebaeba3a04fbfd01b3a5e5a37af61d2f4ce Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* intel/common/smbus: increase spd read performanceKane Chen2017-10-313-0/+48
| | | | | | | | | | | | | | This change increases the spd read performance by using smbus word access. BUG=b:67021853 TEST=boot to os and find 80~100 ms boot time improvement on one dimm Change-Id: I98fe67642d8ccd428bccbca7f6390331d6055d14 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/22072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/intel/apollolake: Switch to common p2sbLijian Zhao2017-10-275-104/+2
| | | | | | | | | | | | | Using common p2sb driver instead of private one. TEST=Boot up into OS, and read back registers through PCR by iotools, return is not 0xffffffff. Change-Id: I30f3ef7bc37a8cb268af6fe2e4da3ec835c17633 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/intel/cannonlake: Use common p2sb driverLijian Zhao2017-10-272-0/+4
| | | | | | | | | | | | | Add common p2sb driver support. TEST=Boot up into OS and read back pcr mmio address by iotools, return is not 0xffffffff. Change-Id: Ida66663e6daabfcb94d7e3224d75b118fc7cf829 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* intel/common/p2sb: Add common p2sb driverLijian Zhao2017-10-274-0/+108
| | | | | | | | | | | | | Add common p2sb device driver that will use fixed resource instead dynamic assigned by PCI enumeration. TEST=None Change-Id: Ie3f7036a5956e3db1662678aaf43023ff79ae10e Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22189 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cannonlake: Add support for C state and P stateShaunak Saha2017-10-263-1/+136
| | | | | | | | | | | | | | | This patch adds the C state and P state configurations for cannonlake soc. TEST = Boot and test the CPU states for all the cores are present in "powertop" tool output. Change-Id: I4ba156354f87646b25d0f9114ebf0583eedf72df Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/21891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/intel/cannonlake: remove duplicate power_state migrationPatrick Georgi2017-10-261-17/+0
| | | | | | | | | | | Common PMC code comes with its own. Change-Id: Ic055f046a2da1c56af4cc7936602d6191ffe7eef Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/22182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/intel/apollolake: avoid double accounting for power statePatrick Georgi2017-10-261-20/+2
| | | | | | | | | | | | | | | | | intel/common's pmclib already keeps track of the power state (since commit f073872e22728fe8ade85022740af95cc129e9a5 and doing it twice can mess up the data that ends up in cbmem (and from there, everything else), so don't. BUG=b:67976359 BRANCH=none TEST=builds Change-Id: I69c804a2a3bee43add940d8c827b7250f2fe9024 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/22179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/intel/apollolake: Fix broken GNVS offset for chromeosFurquan Shaikh2017-10-251-1/+1
| | | | | | | | | | | | | | | | | | Change 03a235(soc/intel/apollolake: Add GNVS variables and include SGX ASL) added new GNVS variables but did not adjust the unused array size and thus broke chromeos offset. This change fixes the above issue by reducing the size of unused array. BUG=b:68254376 TEST=Verified that chromeos offset is correct. crossystem is able to read all variables. Change-Id: I279bfc4c702e46b88c1c7a067a24326ff8fed368 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22177 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/skylake: Fix broken GNVS offset for chromeosFurquan Shaikh2017-10-251-1/+1
| | | | | | | | | | | | | | | | | | | Change 90ebf9 (soc/intel/skylake: Add GNVS variables and include SGX ASL) added new GNVS variables but did not adjust the unused array size and thus broke chromeos offset. This change fixes the above issue by reducing the size of unused array. BUG=b:68254376 TEST=Verified that chromeos offset is correct. crossystem is able to read all variables. Change-Id: I5f76f5bba4f0f50a23a863450743385ad2a82b2b Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22176 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc: Add Kconfig for each soc vendorChris Ching2017-10-231-0/+15
| | | | | | | | | | | | | | | | | | | | | Allows explicit ordering for vendors that share a common configuration that must be sourced last. The issue is that chips in soc/{amd,intel}/[ab].* will be able to override defaults set in this file, but Kconfig files that get sourced later (soc/amd/[d-z].*) will NOT be able to override these defaults. Note: intel and amd soc chips now need to be added manually to the new Kconfig file BUG=b:62235314 TEST=make lint-stable Change-Id: Ida82ef184712e092aec1381a47aa1b54b74ed6b6 Signed-off-by: Chris Ching <chingcodes@google.com> Reviewed-on: https://review.coreboot.org/22123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/intel/cannonlake: Increase stack size from 4KiB to 8KiBJohn Zhao2017-10-231-0/+4
| | | | | | | | | | | | | | | | | | | | | Backtracking stack used BEFORE each function call: 1. cbfs_boot_locate(&file_desc, "vbt.bin", NULL): 4104 (stack overrun) 2. locate_vbt: 4068 3. vbt_get: 4036 4. platforms_fsp_silicon_params_cb: 3924 5. do_silicon_init(&fsps_hdr): 3684 (3684-1092=2592 due to fsps) 6. fsp_silicon_init: 1092 Increase the stack size from 4kiB to 8kiB to prevent stack overrun. TEST=No stack overrun is observed and it boots to OS properly. Change-Id: I7e458b4489cea32449f197621ec81009ea7dd0bd Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21977 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/intel/cannonlake: Change max root port to 16Lijian Zhao2017-10-221-1/+1
| | | | | | | | | | | | Cannonlake SOC support up to 16 PCI express root port. BUG=CID 1381813;1381814; Change-Id: I4df610e3fb01bd8e62be7e9c62144125f2a96c25 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* security/vboot: Move vboot2 to security kconfig sectionPhilipp Deppenwiese2017-10-2213-14/+14
| | | | | | | | | | | | | This commit just moves the vboot sources into the security directory and fixes kconfig/makefile paths. Fix vboot2 headers Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/22074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* soc/intel/skylake: pass SataSpeedLimit param to FSP2Matt DeVillier2017-10-222-0/+3
| | | | | | | | | | | | The Librem13v2 needs to set this parameter to work around power-related issues with some SATA devices. Change-Id: I7fcef36ec8662e18834394b72427a0633c6b7e92 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22045 Reviewed-by: Youness Alaoui <snifikino@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* skylake/me: Add debug output of HFST registersYouness Alaoui2017-10-222-0/+14
| | | | | | | | | | | | The ME status is the interpretation of the status registers, but having the actual status registers printed is important and it doesn't hurt to show them. Change-Id: I6ef3401b36fedfa8aed14f4a62bdbec3d8c6d446 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/21960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* soc/intel/cannonlake: Add platform.aslLijian Zhao2017-10-201-24/+2
| | | | | | | | | | | | | | | Include common platform.asl to have generic indication of power transition state of system. TEST=Enter and resume from S3, check the post code had been changed to 0096 and 0097. Change-Id: Ic38ac6d7e60441caeba5c088c9dbe4d901355782 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22111 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
* soc/intel/skylake: update GNVS with SGX dataPratik Prajapati2017-10-201-0/+4
| | | | | | | | | | | | | - Call sgx_fill_gnvs to update GNVS data, if CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is set. - With this patch SGX ACPI device would get pached with enumaretd values of ECP device status, base address and length Change-Id: Ief0531fbab34838a3f8adb9cdc7d3fe19203c432 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/intel/apollolake: update GNVS with SGX dataPratik Prajapati2017-10-201-0/+4
| | | | | | | | | | | Call sgx_fill_gnvs to update GNVS data, if CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is set. Change-Id: I692f466d2c6f537d44aa042c4890ee8055c982c8 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* intel/common/block/sgx: Add API to enumerate SGX resources and update GNVSPratik Prajapati2017-10-203-0/+51
| | | | | | | | | | | Intel SDM: Table 36-6. CPUID Leaf 12H, Sub-Leaf Index 2 is called to enumerate SGX resources. Change-Id: I62f3fd8527e27040336c52bc78768035f4b7e5a9 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/intel/skylake: Add GNVS variables and include SGX ASLPratik Prajapati2017-10-203-0/+11
| | | | | | | | | | | | | - Add GNVS variables for SGX - Include SGX ASL if CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is set - With this patch SGX ACPI device would get created and kernel SGX driver would let loaded Change-Id: Ie95eb79a01e1c0005e0f137b015b7fe000c1ab2a Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/intel/apollolake: Add GNVS variables and include SGX ASLPratik Prajapati2017-10-203-1/+12
| | | | | | | | | | | | | - Add GNVS variables for SGX - include SGX ASL if CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is set - With this patch SGX ACPI device would get created and kernel SGX driver would let loaded Change-Id: I112cad3cd871082b1884787084c4cc0ebdc7d08f Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* intel/common/acpi: Add common SGX ASLPratik Prajapati2017-10-201-0/+73
| | | | | | | | | | | | - Add EPC device for SGX. Kernel SGX driver expects EPC device. - Hid is INT0E0C - version of the object is 1.0, so _STR is "Enclave Page Cache 1.0" Change-Id: I9efba46469a125ea99241b04fe1ae550d6e03598 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/intel/cannonlake: Fix HECI error on resetLijian Zhao2017-10-194-8/+10
| | | | | | | | | | | | | | | Move HECI init from bootblock to romstage, the HECI bar saved by CAR_GLOBAL, which will be lost on different stage. HECI BAR in ramstage will be read back from PCI. Also add fail safe option to reset in case of HECI command not successful. TEST= Force global reset from FSP and read back HECI bar in debug print. Change-Id: I46c4b8db0a80995fa05e92d61357128c2a77de4b Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/intel/cannonlake: Use EBDA structure to store soc reserve memory sizeSubrata Banik2017-10-192-3/+5
| | | | | | | | | | | | | | | | | | | Avoid calling calculate_dram_base() function to get chipset reserved memory size during pci resource allocation. Rather use EBDA to store chipset reserved memory size while calling cbmem_top_int(). This patch avoids one extra calculate_dram_base() call. BRANCH=none BUG=b:63974384 TEST=Ensures DRAM based resource allocation has taken care of Intel SoC reserved ranges. Change-Id: I2771ea55253ca7d16cd2e2951889ab092b47a9b1 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22099 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/skylake: Use EBDA structure to store soc reserve memory sizeSubrata Banik2017-10-192-4/+6
| | | | | | | | | | | | | | | | | | | Avoid calling calculate_dram_base() function to get chipset reserved memory size during pci resource allocation. Rather use EBDA to store chipset reserved memory size while calling cbmem_top_int(). This patch avoids one extra calculate_dram_base() call. BRANCH=none BUG=b:63974384 TEST=Ensures DRAM based resource allocation has taken care of Intel SoC reserved ranges. Change-Id: I52f359db5a712179d7f2accb4d323d759f3b052b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/22098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/intel/cannonlake: Add IGD Support and pre-OS display codeAbhay Kumar2017-10-193-0/+81
| | | | | | | | | | | | | | | | 1. Add IGD opregion initialization. 2. Use frame buffer return by FSP for display. 3. Derived from "src/soc/intel/apollolake/graphics.c" with changes needed for CNL. TEST=Pre-OS screen comes up and VBT is getting passed to kernel. Change-Id: I19c0cf6cfc03fc9df9e98c75af4e486cb5a19e32 Signed-off-by: Abhay Kumar <abhay.kumar@intel.com> Reviewed-on: https://review.coreboot.org/21999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/fsp_broadwell_de: Add support for GPIO handlingWerner Zeh2017-10-197-0/+275
| | | | | | | | | | | Add functionality to initialize, set and read back GPIOs on FSP based Broadwell-DE implementation. Change-Id: Ibbd86e2142bbf5772eb4a91ebb9166c31d52476e Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/22034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* soc/intel/skylake: Probe XHCI for wake source for Internal PMEFurquan Shaikh2017-10-191-0/+10
| | | | | | | | | | | | | | | | | If GPE_STS indicates that the wake source is internal PME, but none of the controllers have the PME_STS bit set, then try probing individual XHCI ports to see if one of those was a wake source. In some cases e.g. gsmi logging with S0ix, pci_pm_resume_noirq runs before gsmi callback and clears PME_STS_BIT in controller register. In such cases, xhci port status might provide a better idea about the wake source. BUG=b:67874513 Change-Id: I841bb2abccfa9bd6553c1513e88a6306b40315e4 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/22089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-21 16:35:54 +0000