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* src/soc/mediatek: Remove unused <delay.h>Elyes HAOUAS2022-01-052-2/+0
| | | | | | | | Change-Id: I414ad3824819f441f316567795999ed9539cba7b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60603 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* src: Drop duplicated includesElyes HAOUAS2022-01-012-2/+0
| | | | | | | | | | | <types.h> already provides <commonlib/bsd/cb_err.h>, <limits.h>, <stdbool.h>, <stdint.h> and <stddef.h> headers. Change-Id: I700b3f0e864ecce3f8b3b66f3bf6c8f1040acee1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* soc/mediatek/mt8186: Add support for regulator VRF12/VCN33Rex-BC Chen2022-01-011-0/+2
| | | | | | | | | | | | | | To provide power to PS8640, the eDP bridge IC on krabby, add control of VRF12 and VCN33 to set voltage from MT6366. TEST=measure 1.2V from VRF12 and 3.3V from VCN33. BUG=b:210806060 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I55a9ca16e1e335e9355d0a1b30c278a9969db197 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek: Prevent passing NULL MIPI commandsYu-Ping Wu2021-12-281-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Previously (before CB:56965 [1]) mtk_dsi_send_init_command() would ignore NULL initialization commands passed to it. However, in the current code mipi_panel_parse_init_commands() doesn't check that (see CB:57150 [2]), so we should check it on the caller side from mtk_dsi_init(). [1] b2a1480191 device: Move MIPI panel library from mainboard/google/kukui into common [2] 4757a7ea33 mipi: Make panel init callback work directly on DSI transaction types BUG=b:202871018, b:209930699 TEST=emerge-corsola coreboot BRANCH=none Change-Id: I8196e3b135da273325e2e121523abb7fb230a49c Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
* soc/mediatek/mt8195: Move some definations of devapc to common folderRex-BC Chen2021-12-281-0/+50
| | | | | | | | | | | | | Move some definations of devapc for sharing between MT8195 and MT8186. BUG=b:202871018 TEST=emerge-cherry coreboot; emerge-corsola coreboot; Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ia1769ede790f106a320ead9be7e2a596fe96930a Reviewed-on: https://review.coreboot.org/c/coreboot/+/60394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/medaitek/mt8195: adjust USB phy shift valueRex-BC Chen2021-12-262-3/+17
| | | | | | | | | | | | | | | | | There is a design issue of bit shift which will drop a bit for USB3 phy on MT8195. Therefore, we add this patch to set USB phy registers from value of efuse. BUG=b:211528577 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Signed-off-by: Tianping Fang <tianping.fang@mediatek.corp-partner.google.com> Tested-by: Tianping Fang <tianping.fang@mediatek.corp-partner.google.com> Change-Id: I43cb6c1c795dd181d6eba7f3bc52e4eb1a602081 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60312 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8186: add tracker dumpRex-BC Chen2021-12-141-0/+5
| | | | | | | | | | | | | | | | | | Tracker is a debugging tool, and MT8186 only supports AP tracker. When bus timeout occurs, the system reboots and latches some values which could be used for debugging. This function will be triggered only when it encounters the bug hanging issue. BUG=b:202871018 TEST=range of registers are dumped as expected. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ie023de2a6f7421a16b2516baa0bf0bf6fff589e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek: add support for tracker version oneRex-BC Chen2021-12-146-109/+164
| | | | | | | | | | | | | | | | | There are two versions for tracker system: Version 1 for MT8186, and version 2 for MT8192 and MT8195. Reference document: MT8169_bus_dbg_tracker_cfg_reg.xls from MediaTek internal. BUG=b:202871018 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Idb146974da118b1cf5a349370bf7b2fa13f1aba8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59989 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Flush cache before triggering EC resetRex-BC Chen2021-11-291-0/+4
| | | | | | | | | | | | | | | There will be no log in cbmem if we trigger ec reset on bootblock stage. Therefore, call dcache_clean_all() before triggering ec reset to flush cache to store logs on cbmem. BUG=b:207743045 TEST=show logs on cbmem Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I1bd900beb4cc84f7121c5fb66907fa73b62517fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/59683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/medaitek: add prompt string to config MTK_DFDRex-BC Chen2021-11-291-3/+4
| | | | | | | | | | | | | Add prompt string to allow selecting MTK_DFD manually. TEST=Select and enable MTK_DFD then successfully built firmware images. BUG=b:207450135 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ied711321efa592cf1bf7b318fe4d0aa155c15c70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/i2c: Return negative values on errorYu-Ping Wu2021-11-262-19/+18
| | | | | | | | | | | | | | | Following coreboot's convention, return negative error codes from platform_i2c_transfer(). BUG=none TEST=emerge-asurada coreboot BRANCH=none Change-Id: I955b9aae11e20d75fac414d15714330e364dad2f Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/corsola: Add VPROC12/VSRAM_PROC12 to regulator interfaceRex-BC Chen2021-11-261-0/+2
| | | | | | | | | | | | | | Add VPROC12/VSRAM_PROC12 to adjust power for raising little CPU frequency. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I59b4627220022a51a116716036a8ba0048039508 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek: log watchdog statusRex-BC Chen2021-11-261-0/+2
| | | | | | | | | | | | | Reveal watchdog status value on bootblock stage. BUG=b:207646327 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I2c5ad222a41085616565dd5c10b0e967bb64ec63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek: move i2c function to common folderRex-BC Chen2021-11-172-1/+256
| | | | | | | | | | | | | | | Move mtk_i2c_max_step_cnt, mtk_i2c_check_ac_timing, mtk_i2c_speed_init and mtk_i2c_calculate_speed to common folder to share with MT8186. TEST=test on tomato ok TEST=emerge-asurada coreboot BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I4a702741c763bf9261cea90d0d71c08b6e28c261 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: add early initialization for eMMCRex-BC Chen2021-11-161-1/+1
| | | | | | | | | | | | | | | Some eMMCs need 80+ms for CMD1 to complete. And the payload may need to access eMMC in the very early stage (for example, depthcharge needs it 20ms after started) so we have to start initialization in coreboot. TEST=boot kernel from eMMC ok BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I3bc06b1fc506b1d6f54f7f456117d22477a87e29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: Configure eMMC and SD CardWenbin Mei2021-11-161-3/+5
| | | | | | | | | | | | | | The Corsola reference design has both eMMC and SD Card interfaces so we have to configure both in RAM stage. TEST=build pass BUG=b:202871018 Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Change-Id: I2f26a8a11edd29a80a7195e3a324151d66ecb293 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/corsola: Add VMCH and VMC for regulator interfaceRex-BC Chen2021-11-151-0/+2
| | | | | | | | | | | | | Add VMCH and VMC for providing power of SDCard. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I50fc87415086eb22ff35d157dba38cfd7594cc40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59255 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/corsola: Implement regulator interfaceRex-BC Chen2021-11-151-1/+2
| | | | | | | | | | | | | Use regulator interface to use regulator more easily. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ied43cba51036c62a120df2afffeb63b5d73f012b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek: move functions of mmu operation to common folderRex-BC Chen2021-11-151-0/+38
| | | | | | | | | | | | | | Move mtk_soc_disable_l2c_sram and mtk_soc_after_dram to common folder which are the same between MT8192, MT8195 and MT8186. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I8f49214b932a8d28ed2ca0d764dc745fa8ad330d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: Add support for PMIC MT6366James Lo2021-11-152-4/+14
| | | | | | | | | | | | | Add basic support for VCORE/VDRAM1/VDDQ of MT6366. TEST=build pass BUG=b:202871018 Signed-off-by: James Lo <james.lo@mediatek.corp-partner.google.com> Change-Id: I22e30421560a32f4a9e15899e8150376b1414494 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek: Add an overridable function for WDT clear statusRex-BC Chen2021-11-033-8/+4
| | | | | | | | | | | | | | | mtk_wdt_clr_status is different for MT8186 and MT8195, so we move this function to soc folder. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ia8697ffdca1e2d1443f2259713c4ab6fdf1b1a9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58834 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8195: move timer enum variables to timer_v2.hRex-BC Chen2021-11-031-0/+13
| | | | | | | | | | | | | | | Some enum variables of timer v2 are the same between MT8195 and MT8186, so we move them to common timer_v2.h. TEST=emerge-cherry coreboot BUG=b:200134633 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I89891a19e622aa24783025e73c38c4ffa43aa166 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58829 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8195: add tracker dumpZhenguo Li2021-10-132-0/+165
| | | | | | | | | | | | | Tracker is a debugging tool, include AP/INFRA/PERI tracker. When bus timeout occurs, the system reboots and latches some values which could be used for debug. Signed-off-by: Zhenguo Li <ot_zhenguo.li@mediatek.corp-partner.google.com> Change-Id: If457f4a096cd63038bf6b40552aa3caaba33d5fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/58243 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src/soc to src/superio: Fix spelling errorsMartin Roth2021-10-052-2/+2
| | | | | | | | | | | | These issues were found and fixed by codespell, a useful tool for finding spelling errors. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Fix I2C failures by adjusting AC timing and bus speedDaolong Zhu2021-10-022-16/+92
| | | | | | | | | | | | | | | | | | | | | | | | 1. The original algorithm for I2C speed cannot always make the timing meet I2C specification so a new algorithm is introduced to calculate the timing parameters more correctly. 2. Some I2C buses should be initialized in a different speed while the original implementation was fixed at fast mode (400Khz). So the mtk_i2c_bus_init is now also taking an extra speed parameter. There is an equivalent change in kernel side: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/i2c/busses/i2c-mt65xx.c?h=v5.15-rc3&id=be5ce0e97cc7a5c0d2da45d617b7bc567c3d3fa1 BUG=b:189899864 TEST=Test on Tomato, boot pass and timing pass at 100/300/400/500/800/1000Khz. Signed-off-by: Daolong Zhu <jg_daolongzhu@mediatek.corp-partner.google.com> Change-Id: Id25b7bb3a76908a7943b940eb5bee799e80626a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58053 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mipi: Make panel init callback work directly on DSI transaction typesJulius Werner2021-09-112-155/+7
| | | | | | | | | | | | | | | | | | | | | | | Our MIPI panel initialization framework differentiates between DCS and GENERIC commands, but the exact interpretation of those terms is left to the platform drivers. In practice, the MIPI DSI transaction codes for these are standardized and platforms always need to do the same operation of combining the command length and transfer type into a correct DSI protocol code. This patch factors out the various platform-specific DSI protocol definitions into a single global one and moves the transaction type calculation into the common panel framework. The Qualcomm SC7180 implementation which previously only supported DCS commands is enhanced to (hopefully? untested for now...) also support GENERIC commands. While we're rewriting that whole section also fix some other issues about how exactly long and short commands need to be passed to that hardware which we identified in the meantime. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I09ade7857ca04e89d286cf538b1a5ebb1eeb8c04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* soc/mediatek: preserve WDT reset reason for debuggingFengquan Chen2021-09-081-0/+8
| | | | | | | | | | | | | | | | | | 1. Disable external output reset signal in first WDT reset to preserve WDT original reset reason for WDT issue in kernel stage. 2. After preserved WDT reset reason, do fully reset again by sending external output reset signal. BUG=b:194025005 TEST=boot to kernel ok and function test pass Signed-off-by: Fengquan Chen <fengquan.chen@mediatek.corp-partner.google.com> Change-Id: I5887a8312f4daab3cbd0a30fea0195670a932e52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* device/mipi: Move to drivers/mipiJulius Werner2021-08-261-1/+1
| | | | | | | | | | | | | | Sounds like we prefer to have this under drivers/ instead of device/. Also move all MIPI-related headers out from device/ into their own directory. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ib3e66954b8f0cf85b28d8d186b09d7846707559d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* include/bcd: move bcd code to commonlib/bsd/includeRicardo Quesada2021-08-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Move bcd2bin() / bin2bcd() functions to commonlib/bsd/include/ Also, the license is changed from GPL to BSD. This is because it is needed from "utils" (see CL in the chain). For reference bin2bcd() & bcd2bin() are very simple functions. There are already BSD implementations, like these ones (just to name a few): https://chromium.googlesource.com/chromiumos/platform/mosys/+/refs/heads/main/include/lib/math.h#67 http://web.mit.edu/freebsd/head/sys/contrib/octeon-sdk/cvmx-cn3010-evb-hs5.c BUG=b:172210863 TEST=make (everything compiled Ok). Change-Id: If2eba82da35838799bcbcf38303de6bd53f7eb72 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56904 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device: Move MIPI panel library from mainboard/google/kukui into commonJulius Werner2021-08-182-75/+39
| | | | | | | | | | | | | | | | | | | | | | All boards that are trying to use MIPI panels eventually run into the problem that they need to store physical parameters and a list of DCS initialization commands for each panel, and these commands can be very different (e.g. a large amount of very short commands, a few very large commands, etc.). Finding a data format to fit all these different cases efficiently into the same structures keeps being a challenge, and the Kukui mainboard already once put a lot of effort into designing a clean, flexible and efficient solution for this. This patch moves that framework into a common src/device/mipi/ library where it can be used by other boards as well. (Also, this will hopefully allow us to save some duplicated work when using the same panel on different boards at some point.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I877f2b0c7ab984412b288e2ed27f37cd93c70863 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* soc/mediatek/mt8192: move DFD driver to common folderRex-BC Chen2021-08-123-0/+31
| | | | | | | | | | | | | Move DFD driver to common folder so MT8195 can also use it. BUG=b:192429713 TEST=emerge-asurada coreboot Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I7937cddf5f3a66f9269a94301d3134e6f4f9f22e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek: revise the dependency of DVFS config optionsRex-BC Chen2021-08-121-1/+1
| | | | | | | | | | | | The MEDIATEK_DRAM_DVFS_LIMIT_FREQ_CNT only makes sense if DVFS is enabled (e.g., MEDIATEK_DRAM_DVFS) so we should change it to depend on that instead of selecting DVFS. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ib81e4e48e863616ed1e36cd5c0000f4e2cfb5456 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/common: add mt6359p vcore supportJames Lo2021-08-092-0/+12
| | | | | | | | | | | | Add mt6359p vcore set/get support. To adjust frequency of little core, we need to adjust voltage of vcore. Signed-off-by: James Lo <james.lo@mediatek.corp-partner.google.com> Change-Id: Ibf49390ba78870b834c6d0b64e3f0f30f3494f18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56843 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* helpers: Add GENMASK macroYu-Ping Wu2021-08-021-2/+0
| | | | | | | | | | | | | | | | | | | | | | | The GENMASK is defined in multiple files (with various names such as MASKBIT), which sets certain consecutive bits to 1 and leaves the others to 0. To avoid duplicate macros, add GENMASK macro to helpers.h. GENMASK(high, low) sets bits from `high` to `low` (inclusive) to 1. For example, GENMASK(39, 21) gives us the 64-bit vector 0x000000ffffe00000. Remove duplicate macro definitions. Also utilize GENMASK for _BF_MASK in mmio.h. BUG=none TEST=make tests/commonlib/bsd/helpers-test TEST=emerge-cherry coreboot BRANCH=none Change-Id: If2e7c4827d8a7d27688534593b556a72f16f0c2b Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* soc/mediatek/mt8195: Add dramc_param.hRyan Chuang2021-07-071-152/+0
| | | | | | | | | | | | The dramc_param.h defines the header version, structure and APIs for the DRAM calibration parameters stored on the flash, and should be platform independent. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: Ib8a6ea1b6cf1538854890b653d5d9a934f7f687e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/common: Add DPM_FOUR_CHANNEL optionRyan Chuang2021-06-233-14/+39
| | | | | | | | | | | Add DPM_FOUR_CHANNEL option for 4 channel configuration for DPM. Publicize reset_dpm() as dpm_reset() for external reference. Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: If6e0d5c4d16a7ddd69c4a427488f8899870db327 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8195: add power and power control for eDPJitao Shi2021-06-101-0/+2
| | | | | | | | | | | | | | 1. Add API of TVD_PLL1 mt_pll_set_tvd_pll1_freq() for setting rate. 2. Add API of TVD_PLL1 edp_mux_set_sel() for mux sel. 3. Add eDP power domain control. BUG=b:189985956 Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Change-Id: I9e43e0ffeb7b8bcd1786a8d2f5acbf22d5ab501f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55346 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Extract spm_parse_firmware to commonRex-BC Chen2021-06-042-0/+64
| | | | | | | | | | | | | spm_parse_firmware can be shared by MT8192 and MT8195. TEST=emerge-asurada coreboot; Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I54d9672aa9ee9078ec9fe3fa4f2e9fe860a50636 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55139 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Move the SSPM driver to commonRex-BC Chen2021-06-012-0/+39
| | | | | | | | | | | | The SSPM driver can be shared by MT8183, MT8192 and MT8195. TEST=emerge-{asurada, kukui} coreboot; Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: If9779853becb298eeeabb3dc6096bc474baae202 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55050 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Move the MT8192 MCUPM driver to commonRex-BC Chen2021-05-262-0/+47
| | | | | | | | | | | | The MPUCM drivers can be shared by MT8192 and MT8195. TEST=emerge-asurada coreboot; Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I07a66bcf5a149582f34df1cfd08b5514fc5c2eb9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek: Remove duplicate enum declarationRex-BC Chen2021-05-141-1/+1
| | | | | | | | | | | | | Remove dram_cbt_mode in dramc_soc.h. TEST=emerge-asurada coreboot Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Idc4a3887c9cc3f77cbdd7282e2977f6df858817d Reviewed-on: https://review.coreboot.org/c/coreboot/+/54209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Xi Chen <xixi.chen@mediatek.com>
* soc/mediatek/mt8195: Add RTC driverYuchen Huang2021-05-101-0/+333
| | | | | | | | | | | | Both mt8192 and mt8195 use MT659P RTC. Move mt8192/rtc.c to common folder and rename to rtc_mt6359p.c. Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: I73ea90512228a659657f2019249e7142c673e68e Reviewed-on: https://review.coreboot.org/c/coreboot/+/53897 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8195: Add clk_buf driverYuchen Huang2021-05-102-0/+209
| | | | | | | | | | | | Both mt8192 and mt8195 use mt6359p clk_buf. But mt8195 clk_buf uses legacy co-clock mode without srclken_rc. Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com> Change-Id: Ie9ee91449a7a14e77231493f807b321b2dbaa6a6 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/53896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8195: Add mtcmos init supportWeiyi Lu2021-05-052-0/+9
| | | | | | | | Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: If7cd1f596f1406fa21d6586510e9956bb9846a6f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek: Move the power domain data under each SoCWeiyi Lu2021-05-052-22/+14
| | | | | | | | | | | | | In follow-up patches, we need to set multiple power domains to power on the display and audio on MT8195. Move the power domain data under each SoC and make power_on() API to support multiple settings. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: I8c3d19f1e9a4e516d674d68989ad509f37e5b593 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52881 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek: Move the common part of SPI drivers to common/Rex-BC Chen2021-05-052-15/+34
| | | | | | | | | | | | | The SPI drivers can be shared by MT8183, MT8192 and MT8195. TEST=emerge-{oak, kukui, asurada, cherry} coreboot; verified on Cherry P0 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I7bb7809a88fbda67eca67ecfde45b9cb5f09dffe Reviewed-on: https://review.coreboot.org/c/coreboot/+/52854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8195: add pmif/spmi/pmic driverRex-BC Chen2021-05-054-1/+54
| | | | | | | | | | | | | | | | | MT8195 also uses mt6359p so we can reuse most drivers. The only differences are IO configuaration, clock setting, and PMIC internal setting related to soc. Reference datasheet: MT6315 datasheet v1.4.2.pdf, RH-D-2019-0616. Reference datasheet: MT6359_PMIC_Data_Sheet_V1.5.docx, RH-D-2018-0205. Change-Id: I73f9c9bf92837f262c15758f16dacf52261dd3a3 Signed-off-by: Henry Chen <henryc.chen@mediatek.com> Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek: Move the common part of PMIC drivers to common/Yidi Lin2021-04-2812-0/+1693
| | | | | | | | | | The PMIC drivers can be shared by MT8192 and MT8195. Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Ie17e01d25405b1e5119d9c70c5f7afb915daf80b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8195: Add timer supportYidi Lin2021-04-265-44/+98
| | | | | | | | | | | | TEST=emerge-{oak, kukui, asurada, cherry} coreboot; verified on Asurada and Cherry P0 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Ic6a87e7d5983bf14ad123de82ed670a22a7be1aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/52541 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8195: Initialize watchdogYidi Lin2021-04-263-1/+10
| | | | | | | | | | | | MT8195 requires writing speical value to mode register to clear status register. This value is invalid on other platforms. We can do this safely in the common watchdog driver. Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Iba5b41f426fc38719bb343a220e0724bff229c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-26 15:24:58 +0000