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* soc/mediatek: Move common definitions to dramc_soc_common.hRex-BC Chen2022-08-031-0/+22
| | | | | | | | | | | | | | Some definitions are the same in dramc_soc.h for MT8192, MT8195 and MT8186, so we move them to dramc_soc_common.h TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I3095333e62abf98de1f2d27033baeeba7a4cad79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66276 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Create GET_TICK_DLY_REG macro for SPI tick delay settingRex-BC Chen2022-07-291-2/+3
| | | | | | | | | | | | | | | MT8188 SPI tick delay setting is moved to `spi_cmd_reg` register which is different from previous SoCs, so we define a macro to get the designated register. TEST=build pass. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ia30e94a8688c0e1c1d4b3d15206f28e5bd8c9bd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66184 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Move common definitions from rtc.h to rtc_reg_common.hRex-BC Chen2022-07-291-0/+134
| | | | | | | | | | | | | | | Move the common definitions to rtc_reg_common.h, so we can reuse those definitions on MT8188. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ia1d916a88b7cb875b35ee5813b7b52d9e98f5009 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66180 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Move struct mtk_auxadc_regs to auxadc_common.hRex-BC Chen2022-07-291-0/+11
| | | | | | | | | | | | | | The AUXADC register definitions are the same for all MediaTek SoCs, so we move struct mtk_auxadc_regs to auxadc_common.h. TEST=build pass. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I48978a93137a7de42f8ea2873be3130cb8f534f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/geralt: Implement regulator interfaceHui Liu2022-07-221-0/+2
| | | | | | | | | | | | | Control regulator more easily with regulator interface. TEST=measure 3.0V in VMCH and VMC. BUG=b:236331724 Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com> Change-Id: I9727475774b3b9a8dcd49e5e60e133f9d745b407 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65875 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google: Use boolean type for "enable" argument for regulatorRex-BC Chen2022-07-211-2/+2
| | | | | | | | | | | | | | | Because 0 and 1 are the only possible values, 1. Change input argument "enable" of mainboard_enable_regulator to bool. 2. Change return value of mainboard_regulator_is_enabled() to bool. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Iae09c5fedf8f7394bfbb677e5aee37ed061304fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65997 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google: Replace some strings in regulator.cRex-BC Chen2022-07-211-3/+2
| | | | | | | | | | | | | | | | From comments of CB:65875, we replace *_vol to *_voltage. s/mainboard_set_regulator_vol/mainboard_set_regulator_voltage/ s/mainboard_get_regulator_vol/mainboard_get_regulator_voltage/ TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Iadf0408e8914d6e32915464f93979978c4634eaf Reviewed-on: https://review.coreboot.org/c/coreboot/+/65994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8188: Add VMCH, VMC support for MT8188Hui Liu2022-07-212-4/+89
| | | | | | | | | | | | | | For MT8188, we need to enable and adjust VMCH and VMC to support SD cards. Therefore, we add VPA and VSIM1 voltage adjustment APIs. TEST=measure 3.0V in VMCH and VMC. BUG=b:236331724 Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com> Change-Id: I03938f9ef17a0bdd615bcbbfc7b59fa5acb8fbfb Reviewed-on: https://review.coreboot.org/c/coreboot/+/65874 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Create a function to check ulposcRex-BC Chen2022-07-212-8/+19
| | | | | | | | | | | | | | We will use the same drivers for checking ulposc in MT8188, so we add a new function pmif_ulposc_check() to common. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I40136eaeb2c08a97cd65bfb8a81f2f24739d4d51 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65841 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Move SPMI device table to SoC folderHui Liu2022-07-133-21/+13
| | | | | | | | | | | | | | | | | The SPMI devices on MT8188 are different from previous SoCs, so we move them to SoC folder. We also move SoC-specific definitions to soc/pmif.h. TEST=build pass BUG=b:233720142 Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com> Change-Id: I666c2a8222a2bd8cd460e2225a7ae48b001da9d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65757 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek: Add mt_pll_set_usb_clock() to enable usb clockRex-BC Chen2022-07-121-0/+1
| | | | | | | | | | | | | | | There are clock settings for usb in mt8195 and mt8188, so we add a new function which is implemented in pll.c to do this. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I40b358b197541bc5281645879553340059829db3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65750 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek: Move FLASH_DUAL_READ to commonRex-BC Chen2022-07-062-1/+8
| | | | | | | | | | | | | | | | | | FLASH_DUAL_READ is a common configuration for all MediaTek SoCs, so we move it to common folder and select it in SoCs' Kconfig. As suggested in CB:58837, we also rename FLASH_DUAL_READ to FLASH_DUAL_IO_READ to reduce confusion. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: If267a332519412a7919c5b7817047fabe4a564c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65620 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek: Move some gpio functions to common/gpio_op.cRex-BC Chen2022-07-062-0/+63
| | | | | | | | | | | | | | | | gpio_set_pull(), gpio_set_pull_pu_pd() and gpio_set_spec_pull_pupd() can be reused for mt8192, mt8195 and mt8186, so move it to new file "gpio_op.c" in common folder. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I81ab9b01ee20fccf3ef29c5902597b5045d3e36a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65641 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Make timer_prepare() a common functionRex-BC Chen2022-07-061-0/+11
| | | | | | | | | | | | | | | timer_prepare() is the same for MT8195 and MT8186, so move it to common folder. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I91a6f4ecc665a058cb7a0ba96c15b27d6dc97d13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65602 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Move wdt_set_req() to common folderBo-Chen Chen2022-07-062-3/+26
| | | | | | | | | | | | | | | | | | | There are more and more variables which are SoC-specific, so add soc/wdt.h for each SoC and rename common/wdt.h to common/wdt_common.h. wdt_set_req() is almost the same for mt8192, mt8195 and mt8186, so move it to a common file wdt_req.c. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I7a334b3e7cd4f24a848dd31aca546dc7236d5fb8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65636 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek: pass access mode to the payloadWenbin Mei2022-06-121-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | Some eMMCs (for example, Kingston-EMMC64G-TX29-HP) may enter the ready state by sending CMD1 twice. If it is in the ready state, then the payload (for example, depthcharge) will not send CMD1, but the access mode is only available from the response of CMD1. Therefore, we need to pass the access mode to the payload by defining the following types: - MMC_STATUS_CMD1_READY: in ready state and access mode is byte mode. - MMC_STATUS_CMD1_READY_HCS: in ready state and access mode is sector mode. BUG=b:234672726 BRANCH=cherry TEST=boot ok Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com> Change-Id: Iad905781d8ba0105911cf87a6b845cd8df57521e Reviewed-on: https://review.coreboot.org/c/coreboot/+/65054 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek: Rename mtk_wdt_preinit() to mtk_wdt_set_req()Rex-BC Chen2022-06-032-1/+4
| | | | | | | | | | | | | | | | | | To simplify the calling sequence for mtk_wdt_preinit() and we always adjust request setting in mtk_wdt_preinit(), we rename mtk_wdt_preinit() to mtk_wdt_set_req() and call it in mtk_wdt_init(). From this modification, we can also enable thermal hardware reset feature (CB:64676, CB:64675) in MT8192 and MT8195. BUG=none TEST=build pass Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I1904ff9387f7677a077068f2c3df923bd642ea3d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: Enable thermal hardware resetRunyang Chen2022-05-281-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Under the current watchdog setting, the system will not reboot when the temperature is too high. To enable thermal hardware reset, we need to enable thermal control request and set it to reboot mode. Note that because thermal throttle (by lowering cpu frequency) is currently enabled, the thermal hardware reset shouldn't be triggered under normal circumstances. This feature is only for new hardware structure for thermal. Therefore, we only need to apply it on MT8192/MT8195/MT8186. This setting is based on thermal and watchdog section of MT8186 Function Specification. BUG=none TEST=emerge-corsola coreboot TEST=thermal hardware reset is working. Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com> Change-Id: Id2ed55e6d4f4eec450bf7c849f726a389eeb6694 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64659 Reviewed-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* CBMEM: Change declarations for initialization hooksKyösti Mälkki2022-05-201-1/+1
| | | | | | | | | | | | | | | | | | There are efforts to have bootflows that do not follow a traditional bootblock-romstage-postcar-ramstage model. As part of that CBMEM initialisation hooks will need to move from romstage to bootblock. The interface towards platforms and drivers will change to use one of CBMEM_CREATION_HOOK() or CBMEM_READY_HOOK(). Former will only be called in the first stage with CBMEM available. Change-Id: Ie24bf4e818ca69f539196c3a814f3c52d4103d7e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/mediatek: Fill coreboot table with PCIe infoJianjun Wang2022-05-201-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to pass PCIe base address to payloads, implement pcie_fill_lb() to fill coreboot table with PCIe info. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Ib2988694f60aac9cbfc09ef9a26d47e01c004406 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek: Demote log level of SPMI clock calibration problem to infoRex-BC Chen2022-05-091-2/+2
| | | | | | | | | | | | | | | | It's expected that the mismatch logs will be shown when doing calibration for spmi clock. If it is failed to do calibration for spmi clock for all data, the system will enter "die". Therefore, we adjust the log level from BIOS_ERR to BIOS_INFO. BUG=b:231531254 TEST=emerge-cherry coreboot Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I148b4aeaaeb10e1c269a8eccbb19e8d8e17e40ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/64090 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/early_init: Fix function return typeJianjun Wang2022-03-313-9/+7
| | | | | | | | | | | | | | | | Fix return type of early_init_get_elapsed_time_us() to comply with the data type of return value. Also replace memset() with struct initializer. Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Fixes: commit 41faa22 (soc/mediatek: Add early_init for passing data across stages) Change-Id: I7c361828362c2dfec91358ad8a420f5360243da0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/mediatek: Ensure PERST# deassertion time follows the specJianjun Wang2022-03-291-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the PCIe CEM specification, the deassertion of PERST# should occur at least 100ms after the assertion. To ensure the 100ms delay requirement is met, calculate the elapsed time since assertion. If it is smaller than 100ms, do an extra delay. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the measured PERST# time: [DEBUG] mtk_pcie_domain_enable: 432517 us elapsed since assert PERST# [INFO ] mtk_pcie_domain_enable: PCIe link up success (17 tries) And the SSD information in boot log is as follows: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Ie2b7b6174abdf951af5796ab5ed141c45f32fc71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62933 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek: Add early_init for passing data across stagesJianjun Wang2022-03-292-0/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for "early_init_data" region, which can be used to store data initialized in an early stage (such as bootblock), and retrieve it in later stages (such as ramstage). TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: I01f91b7fe2cbe4f73b5c616bb7aae778dee27d9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63019 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek: Add a configurate "USE_CBMEM_DRAM_INFO"Rex-BC Chen2022-03-292-0/+12
| | | | | | | | | | | | | | | | | The memory initialization reference code didn't support returning DRAM information in the old platforms, for example MT8192 and MT8195. So we have to add a new configuration USE_CBMEM_DRAM_INFO to make sure the common code will try to get DRAM information on new platforms supporting that. BUG=none TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Iebe9ea0c1d01890b09fdf586813d85adde9702e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek: Include 'console/console.h' when appropriateElyes HAOUAS2022-03-272-0/+2
| | | | | | | | | | | | Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) Change-Id: I93f930de5a2a477ec4c0d8e5c8c57b25f5e4252c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Xixi Chen <xixi.chen@mediatek.corp-partner.google.com>
* src/soc/mediatek: Remove unused <console/console.h>Elyes HAOUAS2022-03-271-1/+0
| | | | | | | | | | | Found using: diff <(git grep -l '#include <console/console.h>' -- src/) <(git grep -l 'console_time_report\|console_time_get_and_reset\|do_putchar\|vprintk\|printk\|console_log_level\|console_init\|get_log_level\|CONSOLE_ENABLE\|get_console_loglevel\|die_notify\|die_with_post_code\|die\|arch_post_code\|mainboard_post\|post_code\|RAM_SPEW\|RAM_DEBUG\|BIOS_EMERG\|BIOS_ALERT\|BIOS_CRIT\|BIOS_ERR\|BIOS_WARNING\|BIOS_NOTICE\|BIOS_INFO\|BIOS_DEBUG\|BIOS_SPEW\|BIOS_NEVER' -- src/) |grep "<" Change-Id: Ifc85ed8b5660eca11be50fddda0cf32aa1dd611c Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* src: Remove unused <bootmode.h>Elyes HAOUAS2022-03-271-1/+0
| | | | | | | | | | | Found using: diff <(git grep -l '#include <bootmode.h>' -- src/) <(git grep -l 'platform_is_resuming\|gfx_set_init_done\|gfx_get_init_done\|display_init_required\|get_ec_is_trusted\|get_lid_switch\|get_wipeout_mode_switch\|clear_recovery_mode_switch\|get_recovery_mode_retrain_switch\|get_recovery_mode_switch\|get_recovery_mode_retrain_switch\|get_recovery_mode_switch\|get_write_protect_state\|init_bootmode_straps' -- src/) |grep "<" Change-Id: I2ebd472e0cfc641bd7e465b8d29272fd2f7520a1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* soc/mediatek/i2c.c: Remove unused variablesArthur Heymans2022-03-251-9/+0
| | | | | | | | | Change-Id: Iaa643feb76530cc74acf4d714d8a7f96709be1cf Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63023 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* soc/mediatek: Save dram info to cbmemXi Chen2022-03-232-0/+49
| | | | | | | | | | | | | Store dram info in cbmem for ramstage or payloads to use. BUG=b:206014043 TEST=Build pass on Kingler Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I195187c0c757a43bb6d2c57c8f303249f2a7995a Reviewed-on: https://review.coreboot.org/c/coreboot/+/61334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: Disable unused spm_thermalRex-BC Chen2022-03-181-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | In MT8186, we need to disable spm_thermal to prevent it from influencing other wdt status. There are two hardware pathes which are used for asserting watchdog from thermal. We can disable status of path 1 because status of path 2 is used. 1. Thermal -> SPM -> WDT 2. Thermal -> WDT Spm_thermal (path 1) is a flexible option for software control, and the hardware designer suggests that we should disable it if we don't use it. BUG=none TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I0ffde6bad3000a64e3b5782edaa72c62da034302 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62890 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Trigger wdt SW reset when wdt status is not equal to 0Rex-BC Chen2022-03-181-10/+13
| | | | | | | | | | | | | | | Because we close external signal in kernel driver since MT8195, it's more reasonable to trigger sw reset with exteranl signal again whenever the wdt status is not equal to 0. BUG=none TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ic6128df7eadaebcf7ff8d4c5492e3e0cfbab6e36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62797 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: PCI: Remove global variableJianjun Wang2022-03-161-15/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove global variable and use 'pcidev_path_on_root()' to get the base address of PCIe controller. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Ia41c82a7aa5d6e9d936e242550851cef83afeae9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek: Add chip config for setting PCIe configJianjun Wang2022-03-162-66/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | Add chip config for setting PCIe config. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Icff83f2a9f76862065987a74cfcc7e511be80a20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* i2c: Add configurable I2C transfer timeoutJes Klinke2022-03-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces CONFIG_I2C_TRANSFER_TIMEOUT_US, which controls how long to wait for an I2C devices to produce/accept all the data bytes in a single transfer. (The device can delay transfer by stretching the clock of the ack bit.) The default value of this new setting is 500ms. Existing code had timeouts anywhere from tens of milliseconds to a full second beween various drivers. Drivers can still have their own shorter timeouts for setup/communication with the I2C host controller (as opposed to transactions with I2C devices on the bus.) In general, the timeout is not meant to be reached except in situations where there is already serious problem with the boot, and serves to make sure that some useful diagnostic output is produced on the console. Change-Id: I6423122f32aad1dbcee0bfe240cdaa8cb512791f Signed-off-by: Jes B. Klinke <jbk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62278 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* soc/mediatek/common: Add halt() after triggering wdt resetRex-BC Chen2022-03-151-11/+21
| | | | | | | | | | | | | | It's more reasonable to halt when we trigger watchdog reset because the whole system should be reset afterwards. BUG=b:222217317 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I726ba1599841f63b37062f9ce2e04840e4f250bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/62752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: Add GPIO driving functionsGuodong Liu2022-03-091-0/+29
| | | | | | | | | | | | | | | | | | | | | Add GPIO driving functions to adjust pin driving. The value of drive strength is different for each SoC, so we define GPIO_DRV0 to GPIO_DRV7 which are corresponding to 2/4/6/8/10/12/14/16mA in MT8186. This implementation is according to chapter 5.1 in MT8186 Functional Specification. BUG=b:218775654, b:216462313, b:212375511 TEST=build pass Signed-off-by: Guodong Liu <guodong.liu@mediatek.corp-partner.google.com> Change-Id: I6d987f28be98b515fa5c542222bda08bea1d5118 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62471 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* commonlib/bsd: Remove cb_err_tJulius Werner2022-03-091-1/+1
| | | | | | | | | | | | | | | | | cb_err_t was meant to be used in place of `enum cb_err` in all situations, but the choice to use a typedef here seems to be controversial. We should not be arbitrarily using two different identifiers for the same thing across the codebase, so since there are no use cases for serializing enum cb_err at the moment (which would be the primary reason to typedef a fixed-width integer instead), remove cb_err_t again for now. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Iaec36210d129db26d51f0a105d3de070c03b686b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62600 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/mediatek: Add PCIe supportJianjun Wang2022-03-093-0/+278
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PCIe support for MediaTek platform. Reference: - MT8195 Register Map V0.3-2, Chapter 3.18 PCIe controller (Page 1250) - linux/drivers/pci/controller/pcie-mediatek-gen3.c This code is based on MT8195 platform, but it should be common in each platform with the same PCIe IP in the future. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek: remove unused RTC_GPIO_USER_MASKRex-BC Chen2022-03-021-2/+0
| | | | | | | | | | | | | RTC_GPIO_USER_MASK is not used in any drivers, so we remove them. BUG=none TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I0a15d5da142bb38feb595610d69566330e31fedd Reviewed-on: https://review.coreboot.org/c/coreboot/+/62457 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* src/mediatek: Refactor dramc_param to share more structuresXi Chen2022-02-231-0/+73
| | | | | | | | | | | | | The ddr_base_info struct, which stores basic DDR information, should be platform independent. Currently the struct is defined in each SoC's dramc_parah.h. To prevent code duplication, move it as well as other related structs and enums to a common header. Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I99772427f9b0755dc2c778b5f4150b2f8147bcc3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek: Fix printing SPM versionYu-Ping Wu2022-02-121-1/+3
| | | | | | | | | | | | | | | | | Currently the SPM version string is stored at the end of the blob, possibly without a trailing '\0'. Therefore, we should be careful not to print characters beyond the blob size. BUG=b:211944565 TEST=emerge-corsola coreboot TEST=SPM version looked good in AP console BRANCH=asurada,cherry Change-Id: Icfeb686539dc20cf5b78de77c27bdbb137b5d624 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* soc/mediatek: Only update required bits when triggering WDT resetRex-BC Chen2022-02-111-1/+1
| | | | | | | | | | | | | | To prevent to modify original value of wdt_mode, we use setbits32 to update required bits. BUG=b:218420108 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I743c1af3583c18ec8500fc1eb89f31cdbce5317c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61729 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8186: Fix issue of clearing watchdog statusRex-BC Chen2022-02-092-3/+3
| | | | | | | | | | | | | | | The implementation of clearing watchdog status is wrong in CB:58835. The value written to the 'wdt_mode' register should be 'wdt_mode | 0x22000000' instead of 'wdt_status | 0x22000000'. BUG=b:204229208 TEST=check watchdog status is cleared. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I8c5dbaab2ac43d3867037bc4160aa5af2d79284f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: Support DRAM fast calibration using blobXi Chen2022-02-092-23/+55
| | | | | | | | | | | | | | | | | | | | | For most MediaTek SoCs (MT8183, MT8192, MT8195) we rely on an external program (e.g., the "DRAM blob") to do the full DRAM calibration first, then store and and apply the generated parameters to the reference "fast DRAM calibration" in the vendor/mediatek folder for normal system boot. Starting with MT8186 the implementation of fast calibration may need to be changed, and a "DRAM blob" only path is introduced for devices that have to do both full and fast calibration using the external blob. TEST=fast calibration pass on kingler/krabby BUG=b:204226005 Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: If25a7dd6aa6261ecff79a1b4df8b1f2e53d896dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/61133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* treewide: Remove "ERROR: "/"WARN: " prefixes from log messagesJulius Werner2022-02-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Now that the console system itself will clearly differentiate loglevels, it is no longer necessary to explicitly add "ERROR: " in front of every BIOS_ERR message to help it stand out more (and allow automated tooling to grep for it). Removing all these extra .rodata characters should save us a nice little amount of binary size. This patch was created by running find src/ -type f -exec perl -0777 -pi -e 's/printk\(\s*BIOS_ERR,\s*"ERROR: /printk\(BIOS_ERR, "/gi' '{}' ';' and doing some cursory review/cleanup on the result. Then doing the same thing for BIOS_WARN with 's/printk\(\s*BIOS_WARNING,\s*"WARN(ING)?: /printk\(BIOS_WARNING, "/gi' Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I3d0573acb23d2df53db6813cb1a5fc31b5357db8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Lance Zhao Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
* soc/mediatek: Save dramc_param header to mrc_cacheXi Chen2022-01-251-8/+5
| | | | | | | | | | | | | | | Fast-k flow may need to re-init header because mrc_cache doesn't store header. Storing header together with dparam data is better for data consistancy. TEST=fast calibration pass on Corsola BUG=b:204226005 Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I22982923dce06c9e770aa4f20f3dcd2f33685d84 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek: Extract dramc_param_header to a common headerXi Chen2022-01-241-0/+29
| | | | | | | | | | | | | | | | To be shared with different SOCs, move the dramc_param_header struct as well DRAMC_PARAM_FLAG and DRAMC_PARAM_CONFIG enums to a common header file dramc_param_common.h. TEST=fast calibration pass BUG=b:204226005 Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I087971799803e47e34c30063b2b0bd0cfc5795ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/61132 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Fix include guard naming for emi.hYu-Ping Wu2022-01-131-3/+3
| | | | | | | | | | | | | | | | | Fix the name of the include guard for soc/mediatek/common/include/soc/emi.h. BUG=none TEST=emerge-corsola coreboot BRANCH=none Change-Id: Iddac3467959545b7db141545aaa2a135536f44f1 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Xi Chen <xixi.chen@mediatek.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
* src/soc/mediatek: Remove unused <timer.h>Elyes HAOUAS2022-01-101-1/+0
| | | | | | | | Change-Id: Ic87e41a9b317cc7d0b36ece5ffd1d32068e6a33a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-17 21:46:33 +0000