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path: root/src/soc/mediatek/mt8192
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* mb/google/asurada: select mmc storage configWenbin Mei2021-04-091-0/+1
* soc/mediatek: Use MRC cache API for asuradaYu-Ping Wu2021-03-241-0/+1
* soc/mediatek/mt8192: Enlarge ROMSTAGE to 272KYu-Ping Wu2021-03-241-3/+3
* soc/mediatek/mt8192: devapc: Add SCP domain settingTinghan Shen2021-03-223-0/+15
* vendorcode/mt8192: devapc: fix register offset for PCIe domainNina Wu2021-03-171-1/+1
* soc/mediatek/mt8192: adjust i2c "tLOW" and "tSU,STO"Daolong Zhu2021-03-161-3/+29
* soc/mediatek/mt8192: devapc: Add domain remap settingNina Wu2021-03-152-14/+76
* mb/google/asurada: revise PMIC and RTC initializationYidi Lin2021-03-156-29/+2
* soc/mediatek/mt8192: mt6315: revise initial settingHsin-Hsiung Wang2021-03-101-5/+4
* soc/mediatek/mt8192: mt6315: update initial flowHsin-Hsiung Wang2021-03-102-20/+20
* soc/mediatek/mt8192: mt6315: update correct slave idHsin-Hsiung Wang2021-03-101-1/+1
* soc/mediatek/mt8192: Increase PRERAM_CBMEM_CONSOLE to 400KYu-Ping Wu2021-03-081-1/+1
* soc/mediatek/mt8192: initialize DRAM using vendor reference codeHuayang Duan2021-03-0813-12631/+4
* soc/mediatek/common: Move DRAM implementation from mt8192 to commonXi Chen2021-03-0811-531/+53
* mb/google/asurada: Enable RTC for event logYu-Ping Wu2021-02-251-0/+2
* memlayout: Store region sizes as separate symbolsJulius Werner2021-02-191-2/+2
* soc/mediatek: Remove unused <string.h>Elyes HAOUAS2021-02-164-4/+0
* soc/mediatek: Remove unused <console/console.h>Elyes HAOUAS2021-02-153-3/+0
* soc/mediatek/mt8192: Use LZ4 compression for MCUsYu-Ping Wu2021-02-051-1/+1
* soc/mediatek/mt8192/spm.c: Add missing <string.h>Elyes HAOUAS2021-02-041-1/+1
* soc/mediatek/mt8192: Enlarge DRAM_INIT_CODE sizeYu-Ping Wu2021-02-011-5/+10
* mb/google/asurada: Improve boot time by raising little CPU frequencyYidi Lin2021-01-281-0/+2
* soc/mediatek/mt8192: Implement dram all channel calibrationHuayang Duan2021-01-282-0/+357
* soc/mediatek/mt8192: Add mt6315_romstage_initYidi Lin2021-01-282-0/+6
* soc/mediatek/mt8192: Add function to raise the CCI frequencyWeiyi Lu2021-01-281-0/+25
* soc/mediatek/mt8192: pmic: Set efuses manuallyHsin-Hsiung Wang2021-01-222-0/+112
* soc/mediatek/mt8192: pmic: unlock key protection before initial settingHsin-Hsiung Wang2021-01-201-0/+20
* soc/mediatek/mt8192: pmic: add scp voltage initializationHsin-Hsiung Wang2021-01-201-0/+7
* soc/mediatek/mt8192: pmic: enable pwrkey long-press shutdown settingHsin-Hsiung Wang2021-01-191-1/+5
* soc/mediatek/mt8192: pmic: update initial settingHsin-Hsiung Wang2021-01-191-0/+1
* soc/mediatek/mt8192: add clkbuf and srclken_rc MT6359P driverYuchen Huang2021-01-1912-46/+947
* soc/mediatek/mt8192: Save dramc shuffle result after calibrationHuayang Duan2021-01-192-0/+89
* soc/mediatek/mt8192: Add dramc ac timing settingHuayang Duan2021-01-193-0/+1358
* soc/mediatek/mt8192: Get DDR base information after calibrationHuayang Duan2021-01-192-0/+93
* soc/mediatek: rtc: Use `bool` as return typeYidi Lin2021-01-072-12/+13
* soc/mediatek/mt8192: Move flash_controller.c to common/Yidi Lin2020-12-315-299/+12
* soc/mediatek/mt8192: Add DDR mode register initHuayang Duan2020-12-313-1/+408
* soc/mediatek/mt8192: Do dramc duty calibrationHuayang Duan2020-12-312-0/+79
* soc/mediatek/mt8192: Add dramc 8 phase calibrationHuayang Duan2020-12-313-0/+355
* soc/mediatek/mt8192: Update initial settings of dramcHuayang Duan2020-12-313-1/+625
* soc/mediatek/mt8192: eint: unmask eint event mask registerG.Pangao2020-12-304-0/+33
* soc/mediatek/mt8192: Implement dramc base settings for each frequencyHuayang Duan2020-12-291-0/+2926
* soc/mediatek/mt8192: add rtc MT6359P driverYuchen Huang2020-12-284-0/+598
* soc/mediatek/mt8192: devapc: add basic devapc driversNina Wu2020-12-285-0/+117
* soc/mediatek/mt8192: Do dramc pre-settings before calibrationHuayang Duan2020-12-282-0/+278
* soc/mediatek/mt8192: Do dramc software impedance calibrationHuayang Duan2020-12-223-1/+174
* soc/mediatek/mt8192: Do EMI init before dram calibrationHuayang Duan2020-12-222-0/+418
* soc/mediatek/mt8192: Do memory pll init before calibrationHuayang Duan2020-12-222-0/+30
* soc/mediatek/mt8192: Do the dramc pinmux selectionHuayang Duan2020-12-161-0/+102
* soc/mediatek/mt8192: Correct return value of VM18 voltageHsin-Hsiung Wang2020-12-161-1/+1
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