coreboot.git - Coreboot firmware sources

	Commit message (Collapse)	Author	Age	Files	Lines
*	soc/mediatek/mt8195: Add PLL and clock init support	Weiyi Lu	2021-04-28	6	-0/+1876
\| \| \| \| \| \| \| \| \| \| \|	Add PLL and clock init code. Add frequency meter and API for raising little CPU/CCI frequency. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: I8ded0236d10826687f080bd5a213feb55d4bae03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52667 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
*	soc/mediatek/mt8195: Add GPIO driver	Po Xu	2021-04-26	4	-0/+613
\| \| \| \| \| \| \| \|	Signed-off-by: Po Xu <jg_poxu@mediatek.corp-partner.google.com> Change-Id: Ica1b1c80a851075599442298bb6675caf5c72f57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
*	soc/mediatek/mt8195: Add timer support	Yidi Lin	2021-04-26	4	-4/+36
\| \| \| \| \| \| \| \| \| \| \| \|	TEST=emerge-{oak, kukui, asurada, cherry} coreboot; verified on Asurada and Cherry P0 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Ic6a87e7d5983bf14ad123de82ed670a22a7be1aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/52541 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
*	soc/mediatek/mt8195: add register definitions	Yidi Lin	2021-04-26	3	-0/+1445
\| \| \| \| \| \| \| \| \| \|	Add register definitions for infracfg_ao, topckgen, apmixed and SPM. Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Ie740f22aa12f40950a27a3e0142e2d50a506b251 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
*	soc/mediatek/mt8195: Initialize watchdog	Yidi Lin	2021-04-26	3	-0/+8
\| \| \| \| \| \| \| \| \| \| \| \|	MT8195 requires writing speical value to mode register to clear status register. This value is invalid on other platforms. We can do this safely in the common watchdog driver. Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Change-Id: Iba5b41f426fc38719bb343a220e0724bff229c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
*	soc/mediatek/mt8195: Add a stub implementation of the MT8195 SoC	Yidi Lin	2021-04-13	11	-0/+302
	TEST=boot from SPI-NOR and show console message at bootblock stage. Change-Id: Ia93430006096b7410393ab31fee4ea40598d0b34 Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>