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path: root/src/soc/mediatek
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* soc/mediatek/mt8192: Use LZ4 compression for MCUsYu-Ping Wu2021-02-051-1/+1
* soc/mediatek/mt8192/spm.c: Add missing <string.h>Elyes HAOUAS2021-02-041-1/+1
* src: Remove unused <boardid.h>Elyes HAOUAS2021-02-031-1/+0
* soc/mediatek/mt8192: Enlarge DRAM_INIT_CODE sizeYu-Ping Wu2021-02-011-5/+10
* mb/google/asurada: Improve boot time by raising little CPU frequencyYidi Lin2021-01-281-0/+2
* soc/mediatek/mt8192: Implement dram all channel calibrationHuayang Duan2021-01-282-0/+357
* soc/mediatek/mt8192: Add mt6315_romstage_initYidi Lin2021-01-282-0/+6
* soc/mediatek/mt8192: Add function to raise the CCI frequencyWeiyi Lu2021-01-282-0/+26
* soc/mediatek/mt8192: pmic: Set efuses manuallyHsin-Hsiung Wang2021-01-222-0/+112
* soc/mediatek/mt8183: Fix pq module size configYu-Ping Wu2021-01-221-1/+1
* soc/mediatek/mt8192: pmic: unlock key protection before initial settingHsin-Hsiung Wang2021-01-201-0/+20
* soc/mediatek/mt8192: pmic: add scp voltage initializationHsin-Hsiung Wang2021-01-201-0/+7
* soc/mediatek/mt8173/dramc_pi_calibration_api.c: Use __func__Elyes HAOUAS2021-01-191-1/+1
* soc/mediatek/mt8173/pmic_wrap.c: Use __func__Elyes HAOUAS2021-01-191-1/+1
* soc/mediatek/mt8192: pmic: enable pwrkey long-press shutdown settingHsin-Hsiung Wang2021-01-191-1/+5
* soc/mediatek/mt8192: pmic: update initial settingHsin-Hsiung Wang2021-01-191-0/+1
* soc/mediatek/mt8192: add clkbuf and srclken_rc MT6359P driverYuchen Huang2021-01-1912-46/+947
* soc/mediatek/mt8192: Save dramc shuffle result after calibrationHuayang Duan2021-01-192-0/+89
* soc/mediatek/mt8192: Add dramc ac timing settingHuayang Duan2021-01-193-0/+1358
* soc/mediatek/mt8192: Get DDR base information after calibrationHuayang Duan2021-01-192-0/+93
* soc/mediatek/mt8183: Support byte mode and single rank DDRShaoming Chen2021-01-158-141/+459
* soc/mediatek: rtc: Use `bool` as return typeYidi Lin2021-01-078-58/+61
* soc/mediatek: dsi: Fix EoTp flagShaoming Chen2021-01-012-2/+15
* soc/mediatek/mt8192: Move flash_controller.c to common/Yidi Lin2020-12-3110-360/+66
* soc/mediatek/mt8192: Add DDR mode register initHuayang Duan2020-12-313-1/+408
* soc/mediatek/mt8192: Do dramc duty calibrationHuayang Duan2020-12-312-0/+79
* soc/mediatek/mt8192: Add dramc 8 phase calibrationHuayang Duan2020-12-313-0/+355
* soc/mediatek/mt8192: Update initial settings of dramcHuayang Duan2020-12-313-1/+625
* soc/mediatek/mt8192: eint: unmask eint event mask registerG.Pangao2020-12-304-0/+33
* soc/mediatek/mt8192: Implement dramc base settings for each frequencyHuayang Duan2020-12-291-0/+2926
* soc/mediatek/mt8192: add rtc MT6359P driverYuchen Huang2020-12-2812-135/+768
* soc/mediatek/mt8192: devapc: add basic devapc driversNina Wu2020-12-285-0/+117
* soc/mediatek/mt8192: Do dramc pre-settings before calibrationHuayang Duan2020-12-282-0/+278
* soc/mediatek/mt8192: Do dramc software impedance calibrationHuayang Duan2020-12-223-1/+174
* soc/mediatek/mt8192: Do EMI init before dram calibrationHuayang Duan2020-12-222-0/+418
* soc/mediatek/mt8192: Do memory pll init before calibrationHuayang Duan2020-12-223-0/+40
* soc/mediatek/mt8192: Do the dramc pinmux selectionHuayang Duan2020-12-161-0/+102
* soc/mediatek/mt8192: Correct return value of VM18 voltageHsin-Hsiung Wang2020-12-161-1/+1
* soc/mediatek/mt8192: Keep CONN MCU in reset stateWeiyi Lu2020-12-162-0/+9
* soc/mediatek/mt8192: Do dramc init settingsHuayang Duan2020-12-165-1/+239
* soc/mediatek/mt8192: Enable DCMmtk156982020-12-162-0/+77
* soc/mediatek/mt8192: ufs: Disable reference clockWenbin Mei2020-12-165-0/+30
* soc/mediatek/mt8192: Initialize audio pll tuner frequencyWeiyi Lu2020-12-161-0/+4
* soc/mediatek/mt8192: Define DRAM registers and APIsHuayang Duan2020-12-154-0/+5009
* soc/mediatek/mt8192: Add ddp driverYongqiang Niu2020-12-144-0/+482
* soc/mediatek/mt8192: Enable dsi driverHuijuan Xie2020-12-143-0/+58
* soc/mediatek/mt8183: Move dsi driver to common/Yidi Lin2020-12-142-1/+1
* soc/mediatek/mt8192: add i2c driver supportQii Wang2020-12-146-13/+266
* soc/mediatek/mt8192: Init SSPMTingHan.Shen2020-12-106-0/+52
* soc/mediatek/mt8192: Init DPMHuayang Duan2020-12-105-0/+115
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