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path:
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sifive
Commit message (
Expand
)
Author
Age
Files
Lines
...
*
soc/sifive/fu540: Get SDRAM controller out of reset
Philipp Hug
2018-09-13
1
-0
/
+34
*
soc/sifive/fu540: Update clock settings according SiFive bootloader
Philipp Hug
2018-09-13
1
-8
/
+30
*
uart/sifive: make divisor configurable
Philipp Hug
2018-09-13
2
-1
/
+9
*
soc/sifive/fu540: Initialize PLL and clock
Philipp Hug
2018-09-12
2
-0
/
+202
*
soc/sifive: fix compiler warning
Philipp Hug
2018-09-10
1
-1
/
+1
*
soc/sifive/fu540: Makefile: include mtime_init in ramstage
Philipp Hug
2018-09-10
1
-0
/
+1
*
soc/sifive/fu540: Add driver for OTP memory
Philipp Hug
2018-09-10
3
-0
/
+129
*
soc/sifive/fu540: add CLINT support
Xiang Wang
2018-09-10
4
-7
/
+42
*
riscv: update mtime initialization
Xiang Wang
2018-09-10
2
-0
/
+23
*
riscv: separately define stack locations at different stages
Xiang Wang
2018-09-02
1
-2
/
+3
*
sifive/fu540: add empty sdram init and size functions
Philipp Hug
2018-07-18
3
-0
/
+59
*
riscv: add support for modifying compiler options
Xiang Wang
2018-07-17
1
-0
/
+12
*
src/sifive: Add the SiFive Freedom Unleashed 540 SoC
Jonathan Neuschäfer
2018-04-26
9
-0
/
+226
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