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* amd/stoneyridge: Add FCH WAK and PTS methodsMarshall Dawson2018-10-011-0/+58
* amd/stoneyridge: Add ASL for D-states on AOAC devicesMarshall Dawson2018-10-011-0/+154
* amd/stoneyridge: Add ACPI MMIO and PCI offsets to ASLMarshall Dawson2018-10-011-0/+242
* amd/stoneyridge: Load AOAC and USB gnvs valuesMarshall Dawson2018-10-012-0/+51
* amd/stoneyridge: Add USB settings to gnvsMarshall Dawson2018-10-012-1/+11
* amd/stoneyridge: Create gnvs entries for AOAC devicesMarshall Dawson2018-10-013-1/+44
* soc/intel/fsp_broadwell_de: Fix IA32_MC0_* namesElyes HAOUAS2018-10-012-7/+8
* soc/cavium/cn81xx/spi: Add function to return SPI clockPatrick Rudolph2018-09-302-0/+22
* amd/stoneyridge: Make gnvs ASL whitespace consistentMarshall Dawson2018-09-281-13/+13
* soc/amd/stoneyridge/BiosCallOuts: Remove #include <AmdLib.h>Richard Spiegel2018-09-281-1/+0
* soc/intel/cannonlake: Fix ACPI FADT table generationDuncan Laurie2018-09-281-13/+12
* soc/intel/cannonlake: Move SkipMpInit config to FSPMLijian Zhao2018-09-281-0/+4
* soc/amd/common/block/pi: Remove references to AmdLibRichard Spiegel2018-09-282-2/+0
* soc/intel/cannonlake: Add ACPI entry for LANLijian Zhao2018-09-282-1/+33
* soc/intel/cannonlake: Update UPD from device switchLijian Zhao2018-09-282-35/+47
* src/*: normalize Google copyright headersPatrick Georgi2018-09-281-1/+1
* soc/sifive/fu540: Document #if ENV_ROMSTAGE lineJonathan Neuschäfer2018-09-261-3/+2
* soc/sifive/fu540: Remove PLL parameters from sdram.cJonathan Neuschäfer2018-09-261-2/+0
* mb/lowrisc: Remove the Nexys4DDR portJonathan Neuschäfer2018-09-264-65/+0
* soc/intel/common/block: Don't use device_tElyes HAOUAS2018-09-262-2/+2
* amd/common/psp: Remove use of PspBaseLibCharles Marslett2018-09-242-11/+96
* soc/amd/stoneyridge/romstage.c: Move STAPM code to SOC specificRichard Spiegel2018-09-243-0/+27
* skylake,kabylake: Add support to set eMMC tuning param from dev treePratik Prajapati2018-09-222-0/+12
* soc/intel/denverton_ns/csme_ie_kt.c: Don't use device_tElyes HAOUAS2018-09-211-1/+1
* soc/intel/braswell/ramstage.c: Add SoC stepping D-1 supportFrans Hendriks2018-09-212-3/+10
* soc/intel/quark/uart.c: Don't use device_tElyes HAOUAS2018-09-211-1/+1
* soc/intel/skylake: Don't use device_tElyes HAOUAS2018-09-211-1/+1
* soc/broadwell: Don't use device_tElyes HAOUAS2018-09-214-9/+9
* soc/intel/skylake: Include some microcode blobsArthur Heymans2018-09-212-1/+15
* soc/intel/cannonlake: Correct ITSS port id.praveen hodagatta pranesh2018-09-211-1/+1
* soc/intel/cannonlake: Remove const for spd_smbus_addressLijian Zhao2018-09-201-1/+1
* soc/amd/stoneyridge/romstage.c: Remove obsolete commentRichard Spiegel2018-09-201-5/+0
* soc/intel/fsp_broadwell_de: Add fixed VT-d MMIO range to the resourcesWerner Zeh2018-09-202-2/+17
* fsp_broadwell_de: Move DMAR table generation to corresponding VT-d deviceWerner Zeh2018-09-206-10/+40
* amd/stoneyridge: Sync PSP base to MSRMarshall Dawson2018-09-191-0/+17
* soc/intel/common/block: Don't use device_t in ramstageElyes HAOUAS2018-09-187-14/+15
* soc/cavium/cn81xx: Don't use device_t in ramstageElyes HAOUAS2018-09-181-4/+4
* cpu/*/car: fix ancient URL explaining XIP range run-time calculationStefan Tauner2018-09-181-1/+1
* mb/google/kahlee/variants/baseboard: Set STAPM percentageRichard Spiegel2018-09-171-0/+3
* soc/intel/broadwell: Add PCH_GPIO_PIRQ_INVERT definitionMatt DeVillier2018-09-171-0/+5
* sifive/hifive-unleashed: enable CBMEM supportPhilipp Hug2018-09-151-0/+1
* soc/sifive: move ram_resource to mainboardPhilipp Hug2018-09-151-20/+0
* soc/intel/denverton_ns: Enable common block PMCJulien Viard de Galbert2018-09-1411-14/+38
* soc/sifive/fu540: Implement uart_platform_refclk for UART divisor calculationPhilipp Hug2018-09-141-1/+8
* soc/sifive/fu540: Initialize SDRAMPhilipp Hug2018-09-143-1/+240
* soc/sifive/fu540: Switch clock to 1GHz in romstagePhilipp Hug2018-09-142-16/+46
* soc/sifive/fu540: create ram_resource with actual memory sizePhilipp Hug2018-09-141-0/+20
* arch/riscv: provide a monotonic timerPhilipp Hug2018-09-143-0/+10
* soc/sifive/fu540: add SiFive supplied header files for SDRAM initializationPhilipp Hug2018-09-143-0/+1664
* complier.h: add __always_inline and use it in code baseAaron Durbin2018-09-142-4/+2
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