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* src/amd/stoneyridge: Fix a typo (EDGEL_TRIG -> EDGE_TRIG)Jonathan Neuschäfer2018-04-111-1/+1
* amd/stoneyridge: Reorder temp mtrr for flashMarshall Dawson2018-04-111-4/+3
* soc/intel/common/block/cpu: Fix cpu_get_power_maxMario Scheithauer2018-04-111-1/+1
* soc/intel/common/block/gspi: Set Clock Update Bit for clock updates.Shamile Khan2018-04-111-1/+2
* Correct "MTTR" to "MTRR"Jonathan Neuschäfer2018-04-111-10/+10
* soc/intel: Remove superfluous pointers variablesArthur Heymans2018-04-113-10/+7
* soc/intel/common: Configure all possible GFX DSM memory reserve rangeSubrata Banik2018-04-111-1/+26
* soc/intel/apollolake: fix SPI input clock speedAaron Durbin2018-04-101-2/+2
* soc/intel/cannonlake: Set Cannonlake I2C clockLijian Zhao2018-04-101-1/+1
* soc/intel/common: prepare for lpss clock splitAaron Durbin2018-04-107-16/+18
* soc/amd/stoneyridege: Create AP jump structureRichard Spiegel2018-04-105-27/+115
* soc/amd: Add "halt this AP" callback to romstageRichard Spiegel2018-04-102-0/+4
* soc/intel/apollolake: Fix GPIO group to GPE mapping for GLKHannah Williams2018-04-091-6/+6
* soc/intel/apollolake: enable MONITOR/MWAIT for GLKCole Nelson2018-04-092-2/+5
* soc/intel/common: Add funtion to modify PAT & NXE bitNaresh G Solanki2018-04-093-0/+35
* amd/stoneyridge: Add GNB IOAPIC initMarc Jones2018-04-091-0/+10
* soc/intel/{apl,glk}: Move flush_l1d_to_l2 function to common locationNaresh G Solanki2018-04-092-7/+11
* fsp_broadwell_de: Provide valid address and size for DCACHE rangeWerner Zeh2018-04-061-0/+16
* fsp_broadwell_de: Provide valid ACPI path names for domain and LPCWerner Zeh2018-04-062-0/+25
* amd/common/block/pi: Make agesa_heap_base() staticMarshall Dawson2018-04-062-3/+1
* amd/stoneyridge: Use defined value for SPI flash MTRRMarshall Dawson2018-04-062-1/+13
* soc/intel/cannonlake: Add VT-d and VMX programmingLijian Zhao2018-04-053-0/+13
* soc/intel/cannonlake: Clear EMMC timeout when boot source is not EMMCBora Guvendik2018-04-051-4/+24
* mb/amd/gardenia/gpio.c: Convert GPIO to new formatRichard Spiegel2018-04-051-0/+5
* soc/qualcomm/sdm845: Add MMU supportT Michael Turney2018-04-055-1/+85
* soc/qualcomm/sdm845: remove hole in memlayout.ldT Michael Turney2018-04-051-1/+1
* soc/intel/skylake: Generate ACPI DMAR tableNico Huber2018-04-054-1/+78
* soc/intel/skylake: Enable VT-d and X2APICNico Huber2018-04-057-0/+80
* spi: Add helper functions for bit-bangingJulius Werner2018-04-031-0/+157
* rockchip: Add gpio_set() functionJulius Werner2018-04-031-1/+6
* src/soc/stoneyridge: Add a check for CMOS failureMartin Roth2018-04-021-2/+3
* soc/intel/skylake: Save/restore GMA OpRegion addressMatt DeVillier2018-03-303-2/+98
* soc/intel/braswell: Save/restore GMA OpRegion addressMatt DeVillier2018-03-304-1/+98
* soc/intel/common/opregion: Get rid of opregion.cPatrick Rudolph2018-03-3013-203/+15
* soc/intel/skylake: Protect me_progress_rom_values array boundaryKane Chen2018-03-301-2/+8
* soc/intel/skylake: Limit xDCI feature when VBOOT is enabledDuncan Laurie2018-03-284-4/+16
* soc/intel/common/block: add VMX supportMatt DeVillier2018-03-285-0/+107
* soc/intel/cannonlake: Limit xDCI feature when VBOOT is enabledDuncan Laurie2018-03-283-3/+8
* soc/intel/apollolake: Limit xDCI feature when VBOOT is enabledDuncan Laurie2018-03-282-1/+8
* soc/intel/common: Add function to check if xDCI is allowedDuncan Laurie2018-03-282-0/+11
* soc/intel/skylake: enable VMX supportMatt DeVillier2018-03-282-0/+18
* soc/intel/skylake: Add NHLT config for max98373 codecDuncan Laurie2018-03-274-0/+100
* soc/intel/skylake: Do a heci_reset before reading ME firmware versionFurquan Shaikh2018-03-271-0/+6
* soc/qualcomm/sdm845: Support for new SoCT Michael Turney2018-03-269-0/+289
* soc/intel: Add KBL-S MCH and some KBL PCH supportGaggery Tsai2018-03-263-0/+10
* soc/skylake/cpu: Fix Intel SpeedStep enable/disableMatt DeVillier2018-03-261-2/+2
* soc/amd: Print dimm_info and TYPE17_DMI_INFO to help debug incorrect valuesRaul E Rangel2018-03-232-0/+77
* soc/intel/cannonlake: Enable low power S0 Idle capabilityVaibhav Shankar2018-03-232-0/+6
* soc/intel/apollolake: Bypass FSP's deassertion of PERST# signal.Shamile Khan2018-03-231-0/+11
* amd/stoneyridge: Add PM1 wake status to boot logMarshall Dawson2018-03-221-0/+71
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