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* soc/amd: Change Morgana codename to PhoenixMartin Roth2023-01-1259-149/+149
| | | | | | | | | | | | | | | | | | | | | | | Now that the next generation of APUs is officially announced, we can unmask morgana. The chip formerly known as Morgana is actually Phoenix. Surprise! This patch just changes the name across the entire codebase. Note that the fw.cfg file will stay pointing to the 3rdparty/amd_blobs/morgana/psp directory until the amd_blobs_repo is updated. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Ie9492a30ae9ff9cd7e15e0f2d239c32190ad4956 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71731 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common/block/early_graphics: Introduce a 200 ms delayJeremy Compostella2023-01-121-0/+17
| | | | | | | | | | | | | | | | | | | | It has been reported that the PEIM graphics driver may temporarily fail communication with the display if the time between libgfxinit turning off the displays and the PEIM driver initialization is too short. 200 ms has been identified as a safe delay. This is a temporary workaround and an investigation is in progress to come up with a better and long term solution. BUG=b:264526798 BRANCH=firmware-brya-14505.B TEST=Developer screen is systematically seen Change-Id: I4ea15123eed1a4355c5ff7d815925032d4151de1 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71656 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Inform user of memory trainingJeremy Compostella2023-01-122-0/+30
| | | | | | | | | | | | | | | | | | | If memory training is going to happen and early graphics is supported by the mainboard, an on-screen text message is displayed to inform the end user. Memory training can take a while and an impatient end user facing a black screen for a while may reset the device unnecessarily. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=On screen text message during MRC training observed on skolas Change-Id: I4ea15123eed1a4355c5ff7d815925032d4151de0 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70300 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Add romstage early graphics supportJeremy Compostella2023-01-125-0/+54
| | | | | | | | | | | | BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=Verify that VGA text mode is functional in romstage Change-Id: I727b28bbe180edc2574e09bf03f1534d6282bdb2 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70303 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common/block: Add Intel VGA early graphics supportJeremy Compostella2023-01-124-0/+82
| | | | | | | | | | | | | | | | | | | | | | | This patch introduces an early graphics driver which can be used in romstage in cache-as-ram mode. The implementation relies on `libgfxinit' and provide VGA text mode support. SoCs wanting to take advantage of this driver must implement the `early_graphics_soc_panel_init' function to set the panel power sequence timing parameters. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=Graphics bring up observed on skolas with extra patches Change-Id: Ie4ad1215e5fadd0adc1271b6bd6ddb0ea258cb5b Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70299 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Maulik Vaghela <maulikvaghela@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/elkhartlake: Provide a way to enable real-time tuningWerner Zeh2023-01-113-6/+30
| | | | | | | | | | | | | | | | | | | | | | | Intel provides a Real-Time Tuning Guide for Elkhart Lake to improve real-time behaviour of the SoC (see Intel doc #640979). It describes, amongst knobs for the OS, a couple of firmware settings that need to be set properly to reduce latencies in all the subsystems. Things like clock and power gating as well as low power states for peripherals and buses are disabled in this scenario. This patch takes the mentioned UEFI parameters from the guide and translates them to FSP-M and FSP-S parameters. In addition, a chip config switch guards this tuning which can be selected on mainboard level if needed. When this real-time tuning is enabled, the overall system performance in a real-time environment can be increased by 2-3%. Change-Id: Ib524ddd675fb3ea270bacf8cd06cb628e895b4b6 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* soc/intel/meteorlake: Move ME firmware status register structures toDinesh Gehlot2023-01-112-98/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | pertinent header file This patch moves ME host firmware status register structures to ME header file. It also marks unused structure fields to reserved. The idea here is to decouple ME specification defined structures from the source file `.c` and keep those into header files so that in future those spec defined header can move into common code. The current and future SoC platform will be able to select the correct ME spec header based on the applicable config. It might be also beneficial if two different SoC platforms would like to use the same ME specification and not necessarilly share the same SoC directory. BUG=b:260309647 Test=Able to build and boot Google/rex Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ib3dafd6c030c0c848aa82b03bb336cc8fad14de3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71627 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* soc/intel/alderlake: Move ME firmware status register structures toDinesh Gehlot2023-01-112-106/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | pertinent header file This patch moves ME host firmware status register structures to ME header file. It also marks unused structure fields to reserved. The idea here is to decouple ME specification defined structures from the source file `.c` and keep those into header files so that in future those spec defined header can move into common code. The current and future SoC platform will be able to select the correct ME spec header based on the applicable config. It might be also beneficial if two different SoC platforms would like to use the same ME specification and not necessarilly share the same SoC directory. BUG=b:260309647 Test=Able to build and boot Google/brya. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ic14305b0479a8c57531d9930946eded7ac518b09 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71625 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device/Kconfig: Fix selection of software connection managerMartin Roth2023-01-113-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch that introduced the selection of software connection manager, CB:64561 - 060df17f1d (soc/intel/alderlake/acpi: Add Kconfig options for SCM and FCM) added a default to enable the software configuration manager directly in the choice. This leads to warnings when running make menuconfig: src/soc/intel/alderlake/Kconfig:439: warning: defaults for choice values not supported src/soc/intel/meteorlake/Kconfig:337: warning: defaults for choice values not supported src/soc/intel/tigerlake/Kconfig:299: warning: defaults for choice values not supported I'm not sure why the Kconfig linter didn't catch this, but this issue is currently breaking the build for me. This patch fixes it so that instead of setting the default directly, a new Kconfig value is selected that then sets the default correctly. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I674046a93af8f7c2f3003900804deefa89dae295 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71776 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* treewide: stop calling custom TPM log "TCPA"Sergii Dmytruk2023-01-1111-11/+11
| | | | | | | | | | | TCPA usually refers to log described by TPM 1.2 specification. Change-Id: I896bd94f18b34d6c4b280f58b011d704df3d4022 Ticket: https://ticket.coreboot.org/issues/423 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* soc/intel/xeon_sp: Setup DPR for all VT-d devicesJonathan Zhang2023-01-111-2/+4
| | | | | | | | | | | | The Data Protected Range (DPR) needs to be set for all DPR devices, not only the root device. Separate the setup from the memory resource map reservation. Change-Id: I7e49db23960e3938e8e158082be3c5ecf3cf95f3 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* soc/intel/{alderlake,tigerlake}: Fix typo in gpio_defs.hJakub Czapiga2023-01-112-2/+2
| | | | | | | | | | | | Alder Lake and Tiger Lake had unnecessary lower-case 'i' in GPP_C0_IRQ define name. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ida892b00e5a28544950cb9863d0ff2408a514576 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71819 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* drivers/intel/gma: Hook up libgfxinit in romstageJeremy Compostella2023-01-111-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | A mainboard port needs to: - select `CONFIG_MAINBOARD_HAS_EARLY_LIBGFXINIT' - implement the Ada package `GMA.Mainboard' with a single function `ports' that returns a list of ports to be probed for displays. - set the desired `GFX_GMA_DEFAULT_MMIO' IO memory address to use in romstage (and ramstage) for the graphic device. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=libgfxinit compiles in romstage. libgfxinit successfully executes in romstage and ramstage using the requested MMIO setting on skolas. Change-Id: I3c2101de10dc5df54fe873e43bbe0f1c4dccff44 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70276 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/meteorlake: Define SA_DEV_IGD for common codeJeremy Compostella2023-01-111-0/+1
| | | | | | | | | | | | | | | | | SA_DEV_IGD is used by the early graphics feature implemented by the Intel common block. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=Compilation Change-Id: Ic9f0fe1683d55a53c705ae717fe9e40fd8873d1f Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71793 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* soc/intel/elkhartlake/chip.h: Include types.h instead of stdint.hWerner Zeh2023-01-111-1/+1
| | | | | | | | | | | As the used 'bool' type is defined in stdbool.h, include types.h (instead of stdint.h) which includes all needed header files. Change-Id: I3f75776575a7a5f70484411b9f3458530f706ec4 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71790 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common/fsp/Makefile: Fix an error messageAkihiko Odaki2023-01-101-1/+1
| | | | | | | | | | | | | | | It used to say "FSP-M binary larger than FSP_M_FILE", but FSP_M_FILE is the binary itself. The binary file size is actually compared with FSP_M_SIZE. Signed-off-by: Akihiko Odaki <akihiko.odaki@gmail.com> Change-Id: If58069944aea8e68117f2ee1d320726d8c6fdfc8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65440 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* soc/intel: Add Kconfigs to define scaling factor for coresSridhar Siricilla2023-01-106-19/+25
| | | | | | | | | | | | | | | | | | The patch adds Kconfigs to define scaling factor for Efficient and Performance cores instead of using hard coded values in the soc code. Also, the patches uses the Kconfigs directly to calculate the core's nominal performance. So, we don't need to implement soc function soc_get_scaling_factor() to get the scaling factor data for different core types. Hence, soc_get_scaling_factor() function is removed. TEST=Build the code for Gimble and Rex. Also, I have verified that build system logs error when the Kconfigs are undefined. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I55e4d815116ef40c5f33be64ab495e942bf35ee8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71687 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/meteorlake: Use common gpio.h includeDinesh Gehlot2023-01-106-7/+6
| | | | | | | | | | | | | | | | | | Replace the intelblocks/gpio.h, soc/gpio.h and soc/gpio_defs.h includes with the common gpio.h which will include soc/gpio.h which will include intelblocks/gpio.h which will include soc/gpio_defs.h BUG=b:261778357 TEST=Able to build and boot Google/rex. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I58e428cde5e13f4f0dfe528d798c0613b7f8a94a Reviewed-on: https://review.coreboot.org/c/coreboot/+/71630 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* soc/mediatek/common: Reset the watchdog timer before triggering resetRunyang Chen2023-01-102-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | When the watchdog timer reaches 0, the timer value won't reset to the default value unless there is an external reset or a kick. It will result in the watchdog failing to trigger the reset signal. We kick the watchdog to reset the timer to the default value. Also, because WDT hardware needs about 94us to synchronize the registers, add a 100us delay before triggering the reset signal. BUG=b:264003005, b:264017048 BRANCH=corsola TEST= Reboot successfully with the following cmd stop daisydog sleep 60 > /dev/watchdog& Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com> Signed-off-by: Kuan-Hsun Cheng <allen-kh.cheng@mediatek.com> Change-Id: Ic4964103d54910c4a1e675b59c362e93c2213b19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71754 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/elkhartlake: Make SATA speed limit configurableWerner Zeh2023-01-102-0/+9
| | | | | | | | | | | | | | | | | | In cases where there are limitations on the mainboard it can be necessary to limit the used SATA speed even though both, the SATA controller and disk drive support a higher speed rate. The FSP parameter 'SataSpeedLimit' allows to set the speed limit. This patch provides a chip config so that this FSP parameter can be set as needed in the devicetree on mainboard level. Change-Id: I610263b34b0947378d2025211ece4a9ec8fbfef6 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71229 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* treewide: Remove unused <cpu/amd/msr.h>Elyes Haouas2023-01-0915-15/+0
| | | | | | | | Change-Id: Id24a7c7db24f49672df9d5ceefec5b7596f23e09 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd: Remove dummy SOC_SPECIFIC_OPTIONSElyes Haouas2023-01-096-53/+35
| | | | | | | | Change-Id: I080b7b579338c3cf342beabda54f43f525d8b65c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/morgana: Double max number of cpus for morganaRitul Guru2023-01-092-2/+1
| | | | | | | | | Change-Id: I5169a900345e2aabefcf1e2c249ee4bce6dc8fc5 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/morgana: update morgana cpuidRitul Guru2023-01-091-1/+1
| | | | | | | | Change-Id: Ieaad72a6b964f4b2ab572733694def88e30888a3 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/mendocino/Kconfig: Remove TODO after reviewFred Reitberger2023-01-091-20/+18
| | | | | | | | | | | | | | Remove TODO comments after reviewing against mendocino ppr #57243, rev 3.00 BUG=263563246 TEST=build skyrim Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ie56d481dd8b6b4e0a1e3d50f4ce75f50231fe4dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/71719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* soc/amd/common/block/graphics: Fix whitespace consistencyFred Reitberger2023-01-091-6/+6
| | | | | | | | | | | Replace spaces with tabs for consistency. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I65b9bec7443094dfd2f6b0d6b11e0100023873b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/intel/xeon_sp/skx: Remove nested check for ACPI supportMarc Jones2023-01-091-2/+0
| | | | | | | | | | Remove redundant nested check for ACPI support. Change-Id: Ie4b40382d304028135bcdd7851e2f48333570421 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* soc/intel/common: Fix cpu index calculationSridhar Siricilla2023-01-091-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | get_cpu_index() helper function returns cpu's index based on it's APIC id position from the ascending order list of cpus' APIC IDs. In order to calculate the cpu's index, the helper function needs to traverse through each cpu node to find their APIC IDs. So, the function traverse the CPU node list from the cpu whose APIC ID is 0 assuming it is the first cpu node in the list. This logic works fine where BSP's APIC ID is 0. But, starting from MTL, APIC ID for BSP need not be 0 as APIC ID numbering first get assigned for CPU Die Efficient cores, then Performance cores. Please refer section# 6.1 of doc#643504 for more details on APIC IDs. Considering the APIC Id allotment for MTL cores, as existing code traversing begins from the cpu that has APIC Id#0 which may not be the first cpu node in the list so index calculation results in wrong value. The patch addresses above described issue by traversing all the CPU nodes to calculate the cpu index. Also, prevents inconsistent report of /sys/devices/system/cpu/cpu*/cpufreq/* and /sys/devices/system/cpu/cpuXX/acpi_cppc on each reboot. TEST=Verified that the get_cpu_index helper function returns the correct index id for a CPU on Rex. The coreboot log with code instrumentation, before this patch: [DEBUG] my_apic_id:0x10 cpu_index: 0x6 [DEBUG] my_apic_id:0x11 cpu_index: 0x6 [DEBUG] my_apic_id:0x42 cpu_index: 0x6 [DEBUG] my_apic_id:0x21 cpu_index: 0x6 [DEBUG] my_apic_id:0x40 cpu_index: 0x6 [DEBUG] my_apic_id:0x31 cpu_index: 0x6 [DEBUG] my_apic_id:0x39 cpu_index: 0x6 [DEBUG] my_apic_id:0xa cpu_index: 0x3 [DEBUG] my_apic_id:0x0 cpu_index: 0x0 [DEBUG] my_apic_id:0x8 cpu_index: 0x2 [DEBUG] my_apic_id:0x4 cpu_index: 0x2 [DEBUG] my_apic_id:0x28 cpu_index: 0x6 [DEBUG] my_apic_id:0x2 cpu_index: 0x1 [DEBUG] my_apic_id:0x38 cpu_index: 0x6 [DEBUG] my_apic_id:0x29 cpu_index: 0x6 [DEBUG] my_apic_id:0xe cpu_index: 0x5 [DEBUG] my_apic_id:0x6 cpu_index: 0x2 [DEBUG] my_apic_id:0x20 cpu_index: 0x6 [DEBUG] my_apic_id:0x30 cpu_index: 0x6 [DEBUG] my_apic_id:0x19 cpu_index: 0x6 [DEBUG] my_apic_id:0xc cpu_index: 0x4 [DEBUG] my_apic_id:0x18 cpu_index: 0x6 We can see same cpu_index for multiple cores before fix. After this patch.. [DEBUG] my_apic_id:0x10 cpu_index: 0x8 [DEBUG] my_apic_id:019 cpu_index: 0xb [DEBUG] my_apic_id:0x11 cpu_index: 0x9 [DEBUG] my_apic_id:0x18 cpu_index: 0xa [DEBUG] my_apic_id:0x40 cpu_index: 0x14 [DEBUG] my_apic_id:0x30 cpu_index: 0x10 [DEBUG] my_apic_id:0x42 cpu_index: 0x15 [DEBUG] my_apic_id:0xc cpu_index: 0x6 [DEBUG] my_apic_id:0x2 cpu_index: 0x1 [DEBUG] my_apic_id:0x29 cpu_index: 0xf [DEBUG] my_apic_id:0xe cpu_index: 0x7 [DEBUG] my_apic_id:0x20 cpu_index: 0xc [DEBUG] my_apic_id:0x0 cpu_index: 0x0 [DEBUG] my_apic_id:0x31 cpu_index: 0x11 [DEBUG] my_apic_id:0x28 cpu_index: 0xe [DEBUG] my_apic_id:0x21 cpu_index: 0xd [DEBUG] my_apic_id:0xa cpu_index: 0x5 [DEBUG] my_apic_id:0x38 cpu_index: 0x12 [DEBUG] my_apic_id:0x8 cpu_index: 0x4 [DEBUG] my_apic_id:0x4 cpu_index: 0x2 [DEBUG] my_apic_id:0x39 cpu_index: 0x13 Change-Id: I69e5e6231dd18b43d439340aaed50eb9edeca3b7 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70751 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Disable Intel TXT based on `INTEL_TXT` configSubrata Banik2023-01-092-0/+9
| | | | | | | | | | | | | | | | This patch makes the call into TXT lib in order to disable the TXT if SoC user haven't selected the `INTEL_TXT` config. Disabling TXT would be helpful to access VGA framebuffer prior calling into FSP-M. TEST=Able to perform disable_txt and unlock memory which helped to access VGA framebuffer prior calling into FSP-M. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9dd7c5492a5f45eef0dd9e836cc2da1844c78919 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71575 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* soc/intel/common: Untie PRMRR from SGXPratikkumar Prajapati2023-01-083-43/+67
| | | | | | | | | | | | | | | | | PRMRR is used by many Intel SOC features, not just Intel SGX. As of now SGX and Key Locker are the features that need PRMRR. Untie it from Intel SGX specific files and move to common cpulib. Also rename PRMRR size config option. Use the renamed PRMRR size config option to set the PRMRR size. TEST=Able to set PRMRR size using config. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: I0cd49a87be0293530705802fd9b830201a5863c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70819 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
* soc/intel/xeon_sp: select SCO_INTEL_COMMON_BLOCK_TCOJohnny Lin2023-01-082-1/+6
| | | | | | | | | | | | | | | | Also disable TCO timer through calling tco_configure(). If tco_configure() is not called, the TCO timeout would trigger SMI periodically about every 2 seconds with SMM log: "TCO_STS: BIT18 TIMEOUT" Tested=On AC CRB, does not see periodic SMI log. Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: I2d307ad16109ae11862dd5e5acc0f12f47b22582 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
* soc/intel/xeon_sp: Improve final MTRR solutionJonathan Zhang2023-01-081-6/+27
| | | | | | | | | | | | | | | | | | If cbmem_top is not 1M aligned there will be a hole between DPR base and cbmem_top that the allocator will consider as unassigned memory. Resources could incorrectly be assigned to that region and the final MTRR solution will also try to skip that hole, therefore using a lot more variable MTRRs than needed. TESTED on Archer City 2S system: Uses 1 variable MTRR in the final setup instead of 7. Change-Id: I198f8d83bcfcdca3a770bd7f9a7060d5782a49fe Signed-off-by: Arthur Heymans <arthur.heymans@9elements.com> Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
* soc/intel/alderlake/acpi: Add Kconfig options for SCM and FCMSean Rhodes2023-01-086-1/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | Software Connection Manager doesn't work with Linux 5.13 or later, resulting in TBT ports timing out. Not advertising this results in Firmware Connection Manager being used and TBT works correctly. Add Kconfig options to chose between SCM (Software Connection Manager) and FCM (Firmware Connection Manager). FCM is primary, as it's more compatible save for ChromeOS devices as ChromeOS uses SCM. Linux patch: torvalds/linux@c6da62a c6da62a219d028de10f2e22e93a34c7ee2b88d03 Tested with StarBook Mk VI (i7-1260P). Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iac31d37c0873f41f7b14e1051fe214466d1ebdd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* soc/intel/meteorlake: Add support to configure package c-state demotionKapil Porwal2023-01-082-0/+8
| | | | | | | | | | | | | | | | | | | | This patch adds the support to enable/disable package c-state demotion feature from the devicetree based on mainboard requirement. Port of commit 4be8d9e80deb ("soc/intel/adl: Add support to configure package c-state demotion") BUG=none TEST=Boot to the OS on Google/Rex. Snippet from FSP log: [SPEW ] PkgCState Demotion : 0x1 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I0a4b0b181349ce41035524482add4336cf83a68b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/intel/meteorlake: Set max Pkg C-states to AutoKapil Porwal2023-01-082-0/+20
| | | | | | | | | | | | | | | | | | | | This patch configures max Pkg C-state to Auto which limits the max C-state to deep C-state. Port of commit af42906efa72 ("soc/intel/alderlake: Set max Pkg C-states to Auto") BUG=none TEST=Boot to the OS on Google/Rex. Snippet from FSP log: [SPEW ] PkgCStateLimit : 0xFF Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ic403ab83a594b04920d5cf600432939687a2598b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/intel/: Rename small and big cores referencesSridhar Siricilla2023-01-064-26/+26
| | | | | | | | | | | | | | | | | The patch addresses Intel heterogeneous cores as `Efficient` and `Performance` cores instead of `small` and `big` cores. It is to ensure coreboot code has uniform reference to the heterogeneous cores. So, the patch renames all `small` and `big` core references to `efficient` (eff) and `performance` (perf) cores respectively. TEST=Build the code for Brya and Rex boards Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I98c9c0ed86b211d736a0a1738b47410faa13a39f Reviewed-on: https://review.coreboot.org/c/coreboot/+/71639 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* soc/intel/common: Check PRMRR dependent featuresPratikkumar Prajapati2023-01-061-22/+46
| | | | | | | | | | | | | | | | | | | | | | | Add below mentioned functions: is_sgx_configured_and_supported(): Checks if SGX is configured and supported is_keylocker_configured_and_supported(): Checks if Key Locker is configured and supported check_prm_features_enabled(): Checks if any of the features that need PRM are configured and supported. As of now SGX and Key Locker are the only features that need PRM. Also, call check_prm_features_enabled() from get_valid_prmrr_size() to make sure PRM dependent features are enabled and configured before returning PRMRR size. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: I51d3c144c410ce4c736f10e3759c7b7603ec3de9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* soc/intel/common: Add Kconfig option for Intel Key LockerPratikkumar Prajapati2023-01-061-0/+9
| | | | | | | | | | | | Add INTEL_KEYLOCKER Kconfig option. Disable it by default. The specification of Key Locker can be found via document #343965 on Intel's site. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: Ia78e9bfe7ba2fd4e45b4821c95b19b8e580dccab Reviewed-on: https://review.coreboot.org/c/coreboot/+/71118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
* soc/intel/meteorlake: Enable support for common IRQ blockKapil Porwal2023-01-067-164/+249
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since GPIO IO-APIC IRQs are fixed in hardware (RO registers), this patch allows MTL boards to dynamically assign PCI IRQs. This means not relying on FSP defaults, which eliminates the problem of PCI IRQs interfering with GPIO IRQs routed to the same IRQ, when both have selected IO-APIC routing. BUG=none TEST=Build and boot to google/rex. Check dmesg and make sure that there is no regression. IO-APIC interrupts before: 1: IO-APIC 1-edge i8042 8: IO-APIC 8-edge rtc0 9: IO-APIC 9-fasteoi acpi 14: IO-APIC 14-fasteoi INTC1083:00 16: IO-APIC 16-fasteoi idma64.5, ttyS0, intel-ipu6 28: IO-APIC 28-fasteoi idma64.6, pxa2xx-spi.6 29: IO-APIC 29-fasteoi i2c_designware.3 30: IO-APIC 30-fasteoi i2c_designware.4 32: IO-APIC 32-fasteoi idma64.0, i2c_designware.0 33: IO-APIC 33-fasteoi idma64.1, i2c_designware.1 35: IO-APIC 35-fasteoi idma64.2, i2c_designware.2 88: IO-APIC 88-fasteoi ELAN0000:00 89: IO-APIC 89-fasteoi chromeos-ec 99: IO-APIC 99-edge cr50_i2c 106: IO-APIC 106-fasteoi chromeos-ec IO-APIC interrupts after: 1: IO-APIC 1-edge i8042 8: IO-APIC 8-edge rtc0 9: IO-APIC 9-fasteoi acpi 14: IO-APIC 14-fasteoi INTC1083:00 16: IO-APIC 16-fasteoi intel-ipu6 20: IO-APIC 20-fasteoi idma64.5, ttyS0 27: IO-APIC 27-fasteoi idma64.0, i2c_designware.0 28: IO-APIC 28-fasteoi idma64.1, i2c_designware.1 30: IO-APIC 30-fasteoi idma64.2, i2c_designware.2 31: IO-APIC 31-fasteoi i2c_designware.3 32: IO-APIC 32-fasteoi i2c_designware.4 35: IO-APIC 35-fasteoi idma64.6, pxa2xx-spi.6 88: IO-APIC 88-fasteoi ELAN0000:00 89: IO-APIC 89-fasteoi chromeos-ec 99: IO-APIC 99-edge cr50_i2c 106: IO-APIC 106-fasteoi chromeos-ec _PRT before: Package (0x04) ==> 0x001FFFFF, Zero, Zero, 0x10 Package (0x04) ==> 0x001FFFFF, One, Zero, 0x11 Package (0x04) ==> 0x001FFFFF, 0x02, Zero, 0x12 Package (0x04) ==> 0x001FFFFF, 0x03, Zero, 0x13 Package (0x04) ==> 0x001EFFFF, Zero, Zero, 0x10 Package (0x04) ==> 0x001EFFFF, One, Zero, 0x11 Package (0x04) ==> 0x001EFFFF, 0x02, Zero, 0x1B Package (0x04) ==> 0x001EFFFF, 0x03, Zero, 0x1C Package (0x04) ==> 0x001CFFFF, Zero, Zero, 0x10 Package (0x04) ==> 0x001CFFFF, One, Zero, 0x11 Package (0x04) ==> 0x001CFFFF, 0x02, Zero, 0x12 Package (0x04) ==> 0x001CFFFF, 0x03, Zero, 0x13 Package (0x04) ==> 0x0019FFFF, Zero, Zero, 0x1D Package (0x04) ==> 0x0019FFFF, One, Zero, 0x1E Package (0x04) ==> 0x0019FFFF, 0x02, Zero, 0x1F Package (0x04) ==> 0x0017FFFF, Zero, Zero, 0x10 Package (0x04) ==> 0x0016FFFF, Zero, Zero, 0x10 Package (0x04) ==> 0x0016FFFF, One, Zero, 0x11 Package (0x04) ==> 0x0016FFFF, 0x02, Zero, 0x12 Package (0x04) ==> 0x0016FFFF, 0x03, Zero, 0x13 Package (0x04) ==> 0x0015FFFF, Zero, Zero, 0x20 Package (0x04) ==> 0x0015FFFF, One, Zero, 0x21 Package (0x04) ==> 0x0015FFFF, 0x02, Zero, 0x22 Package (0x04) ==> 0x0015FFFF, 0x03, Zero, 0x23 Package (0x04) ==> 0x0014FFFF, Zero, Zero, 0x10 Package (0x04) ==> 0x0014FFFF, One, Zero, 0x11 Package (0x04) ==> 0x0014FFFF, 0x02, Zero, 0x12 Package (0x04) ==> 0x0012FFFF, Zero, Zero, 0x1A Package (0x04) ==> 0x0012FFFF, One, Zero, 0x25 Package (0x04) ==> 0x0012FFFF, 0x02, Zero, 0x19 Package (0x04) ==> 0x0010FFFF, Zero, Zero, 0x17 Package (0x04) ==> 0x0010FFFF, One, Zero, 0x16 Package (0x04) ==> 0x000DFFFF, Zero, Zero, 0x10 Package (0x04) ==> 0x000DFFFF, One, Zero, 0x11 Package (0x04) ==> 0x000BFFFF, Zero, Zero, 0x10 Package (0x04) ==> 0x0008FFFF, Zero, Zero, 0x10 Package (0x04) ==> 0x0007FFFF, Zero, Zero, 0x10 Package (0x04) ==> 0x0007FFFF, One, Zero, 0x11 Package (0x04) ==> 0x0007FFFF, 0x02, Zero, 0x12 Package (0x04) ==> 0x0007FFFF, 0x03, Zero, 0x13 Package (0x04) ==> 0x0006FFFF, Zero, Zero, 0x10 Package (0x04) ==> 0x0006FFFF, One, Zero, 0x11 Package (0x04) ==> 0x0006FFFF, 0x02, Zero, 0x12 Package (0x04) ==> 0x0006FFFF, 0x03, Zero, 0x13 Package (0x04) ==> 0x0005FFFF, Zero, Zero, 0x10 Package (0x04) ==> 0x0004FFFF, Zero, Zero, 0x10 Package (0x04) ==> 0x0002FFFF, Zero, Zero, 0x10 Package (0x04) ==> 0x0001FFFF, Zero, Zero, 0x10 Package (0x04) ==> 0x0001FFFF, One, Zero, 0x11 Package (0x04) ==> 0x0001FFFF, 0x02, Zero, 0x12 Package (0x04) ==> 0x0001FFFF, 0x03, Zero, 0x13 _PRT after: Package (0x04) ==> 0x0001FFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x0002FFFF, 0x00, 0x00, 0x00000011 Package (0x04) ==> 0x0004FFFF, 0x00, 0x00, 0x00000012 Package (0x04) ==> 0x0005FFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x0006FFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x0006FFFF, 0x01, 0x00, 0x00000011 Package (0x04) ==> 0x0006FFFF, 0x02, 0x00, 0x00000012 Package (0x04) ==> 0x0007FFFF, 0x00, 0x00, 0x00000013 Package (0x04) ==> 0x0007FFFF, 0x01, 0x00, 0x00000014 Package (0x04) ==> 0x0007FFFF, 0x02, 0x00, 0x00000015 Package (0x04) ==> 0x0007FFFF, 0x03, 0x00, 0x00000016 Package (0x04) ==> 0x0008FFFF, 0x00, 0x00, 0x00000017 Package (0x04) ==> 0x000BFFFF, 0x00, 0x00, 0x00000013 Package (0x04) ==> 0x000DFFFF, 0x00, 0x00, 0x00000014 Package (0x04) ==> 0x000DFFFF, 0x01, 0x00, 0x00000015 Package (0x04) ==> 0x0010FFFF, 0x00, 0x00, 0x00000016 Package (0x04) ==> 0x0010FFFF, 0x01, 0x00, 0x00000017 Package (0x04) ==> 0x0012FFFF, 0x00, 0x00, 0x00000018 Package (0x04) ==> 0x0012FFFF, 0x01, 0x00, 0x00000019 Package (0x04) ==> 0x0012FFFF, 0x02, 0x00, 0x00000011 Package (0x04) ==> 0x0014FFFF, 0x01, 0x00, 0x00000012 Package (0x04) ==> 0x0014FFFF, 0x00, 0x00, 0x0000001A Package (0x04) ==> 0x0014FFFF, 0x02, 0x00, 0x00000013 Package (0x04) ==> 0x0015FFFF, 0x00, 0x00, 0x0000001B Package (0x04) ==> 0x0015FFFF, 0x01, 0x00, 0x0000001C Package (0x04) ==> 0x0015FFFF, 0x02, 0x00, 0x0000001D Package (0x04) ==> 0x0015FFFF, 0x03, 0x00, 0x0000001E Package (0x04) ==> 0x0016FFFF, 0x00, 0x00, 0x00000014 Package (0x04) ==> 0x0016FFFF, 0x01, 0x00, 0x00000015 Package (0x04) ==> 0x0016FFFF, 0x02, 0x00, 0x00000016 Package (0x04) ==> 0x0016FFFF, 0x03, 0x00, 0x00000017 Package (0x04) ==> 0x0017FFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x0019FFFF, 0x00, 0x00, 0x0000001F Package (0x04) ==> 0x0019FFFF, 0x01, 0x00, 0x00000020 Package (0x04) ==> 0x0019FFFF, 0x02, 0x00, 0x00000021 Package (0x04) ==> 0x001CFFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x001CFFFF, 0x01, 0x00, 0x00000011 Package (0x04) ==> 0x001CFFFF, 0x02, 0x00, 0x00000012 Package (0x04) ==> 0x001CFFFF, 0x03, 0x00, 0x00000013 Package (0x04) ==> 0x001EFFFF, 0x00, 0x00, 0x00000014 Package (0x04) ==> 0x001EFFFF, 0x01, 0x00, 0x00000015 Package (0x04) ==> 0x001EFFFF, 0x02, 0x00, 0x00000022 Package (0x04) ==> 0x001EFFFF, 0x03, 0x00, 0x00000023 Package (0x04) ==> 0x001FFFFF, 0x01, 0x00, 0x00000017 Package (0x04) ==> 0x001FFFFF, 0x02, 0x00, 0x00000014 Package (0x04) ==> 0x001FFFFF, 0x03, 0x00, 0x00000015 Package (0x04) ==> 0x001FFFFF, 0x00, 0x00, 0x00000016 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I013cd5faab6f425ab1af91fe2a36ac3b8aeef443 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/intel/common: Use CPUID_STRUCT_EXTENDED_FEATURE_FLAGS macroPratikkumar Prajapati2023-01-061-4/+6
| | | | | | | | | | | | Use CPUID_STRUCT_EXTENDED_FEATURE_FLAGS macro to get extended CPU capabilities flags using cpuid_ext inline function. Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: If680ffff64e2e1dabded8c03c4042d349a11b635 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71646 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel: Create common function to check PCH slotKapil Porwal2023-01-045-7/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BUG=none TEST=Build and boot to google/taniks. Check dmesg and make sure that there is no regression. Also confirm that there is no change in ACPI _PRT and IO-APCI interrupt assignment. IO-APIC interrupts before and after this patch: 1: IO-APIC 1-edge i8042 8: IO-APIC 8-edge rtc0 9: IO-APIC 9-fasteoi acpi 14: IO-APIC 14-fasteoi INTC1055:00 23: IO-APIC 23-fasteoi idma64.5, ttyS0 37: IO-APIC 37-fasteoi idma64.0, i2c_designware.0 38: IO-APIC 38-fasteoi idma64.1, i2c_designware.1 40: IO-APIC 40-fasteoi idma64.2, i2c_designware.2 41: IO-APIC 41-fasteoi idma64.3, i2c_designware.3 42: IO-APIC 42-fasteoi idma64.4, i2c_designware.4 45: IO-APIC 45-fasteoi idma64.6, pxa2xx-spi.6 77: IO-APIC 77-edge cr50_i2c 100: IO-APIC 100-fasteoi ELAN0000:00 103: IO-APIC 103-fasteoi chromeos-ec _PRT before and after this patch: Package (0x04) ==> 0x0001FFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x0002FFFF, 0x00, 0x00, 0x00000011 Package (0x04) ==> 0x0004FFFF, 0x00, 0x00, 0x00000012 Package (0x04) ==> 0x0005FFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x0006FFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x0006FFFF, 0x02, 0x00, 0x00000012 Package (0x04) ==> 0x0007FFFF, 0x00, 0x00, 0x00000013 Package (0x04) ==> 0x0007FFFF, 0x01, 0x00, 0x00000014 Package (0x04) ==> 0x0007FFFF, 0x02, 0x00, 0x00000015 Package (0x04) ==> 0x0007FFFF, 0x03, 0x00, 0x00000016 Package (0x04) ==> 0x0008FFFF, 0x00, 0x00, 0x00000017 Package (0x04) ==> 0x000DFFFF, 0x00, 0x00, 0x00000011 Package (0x04) ==> 0x000DFFFF, 0x01, 0x00, 0x00000013 Package (0x04) ==> 0x0010FFFF, 0x00, 0x00, 0x00000018 Package (0x04) ==> 0x0010FFFF, 0x01, 0x00, 0x00000019 Package (0x04) ==> 0x0010FFFF, 0x02, 0x00, 0x00000014 Package (0x04) ==> 0x0010FFFF, 0x03, 0x00, 0x00000015 Package (0x04) ==> 0x0011FFFF, 0x00, 0x00, 0x0000001A Package (0x04) ==> 0x0011FFFF, 0x01, 0x00, 0x0000001B Package (0x04) ==> 0x0011FFFF, 0x02, 0x00, 0x0000001C Package (0x04) ==> 0x0011FFFF, 0x03, 0x00, 0x0000001D Package (0x04) ==> 0x0012FFFF, 0x00, 0x00, 0x0000001E Package (0x04) ==> 0x0012FFFF, 0x01, 0x00, 0x0000001F Package (0x04) ==> 0x0012FFFF, 0x02, 0x00, 0x00000016 Package (0x04) ==> 0x0013FFFF, 0x00, 0x00, 0x00000020 Package (0x04) ==> 0x0013FFFF, 0x01, 0x00, 0x00000021 Package (0x04) ==> 0x0013FFFF, 0x02, 0x00, 0x00000022 Package (0x04) ==> 0x0013FFFF, 0x03, 0x00, 0x00000023 Package (0x04) ==> 0x0014FFFF, 0x01, 0x00, 0x00000017 Package (0x04) ==> 0x0014FFFF, 0x00, 0x00, 0x00000024 Package (0x04) ==> 0x0014FFFF, 0x02, 0x00, 0x00000011 Package (0x04) ==> 0x0015FFFF, 0x00, 0x00, 0x00000025 Package (0x04) ==> 0x0015FFFF, 0x01, 0x00, 0x00000026 Package (0x04) ==> 0x0015FFFF, 0x02, 0x00, 0x00000027 Package (0x04) ==> 0x0015FFFF, 0x03, 0x00, 0x00000028 Package (0x04) ==> 0x0016FFFF, 0x00, 0x00, 0x00000012 Package (0x04) ==> 0x0016FFFF, 0x01, 0x00, 0x00000013 Package (0x04) ==> 0x0016FFFF, 0x02, 0x00, 0x00000014 Package (0x04) ==> 0x0016FFFF, 0x03, 0x00, 0x00000015 Package (0x04) ==> 0x0017FFFF, 0x00, 0x00, 0x00000016 Package (0x04) ==> 0x0019FFFF, 0x00, 0x00, 0x00000029 Package (0x04) ==> 0x0019FFFF, 0x01, 0x00, 0x0000002A Package (0x04) ==> 0x0019FFFF, 0x02, 0x00, 0x0000002B Package (0x04) ==> 0x001CFFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x001CFFFF, 0x01, 0x00, 0x00000011 Package (0x04) ==> 0x001CFFFF, 0x02, 0x00, 0x00000012 Package (0x04) ==> 0x001CFFFF, 0x03, 0x00, 0x00000013 Package (0x04) ==> 0x001DFFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x001DFFFF, 0x01, 0x00, 0x00000011 Package (0x04) ==> 0x001DFFFF, 0x02, 0x00, 0x00000012 Package (0x04) ==> 0x001DFFFF, 0x03, 0x00, 0x00000013 Package (0x04) ==> 0x001EFFFF, 0x00, 0x00, 0x00000017 Package (0x04) ==> 0x001EFFFF, 0x01, 0x00, 0x00000014 Package (0x04) ==> 0x001EFFFF, 0x02, 0x00, 0x0000002C Package (0x04) ==> 0x001EFFFF, 0x03, 0x00, 0x0000002D Package (0x04) ==> 0x001FFFFF, 0x01, 0x00, 0x00000016 Package (0x04) ==> 0x001FFFFF, 0x02, 0x00, 0x00000017 Package (0x04) ==> 0x001FFFFF, 0x03, 0x00, 0x00000014 Package (0x04) ==> 0x001FFFFF, 0x00, 0x00, 0x00000015 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ib4fc850228b7ddbf84e2feb2433adff5e4002033 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71236 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/mendocino: Hook up UPD dxio_tx_vboost_enable for PCIe optimizationChris.Wang2023-01-042-0/+5
| | | | | | | | | | | | | | | | | | Add the UPD dxio_tx_vboost_enable for PCIe optimization. It will impact the PCIe signal integrity, need to double-confirm the SI result after enabling this setting. BUG=b:259622787 BRANCH=none TEST=confirm the setting has been set correspondingly with checking the FSP log. Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I05ae5b3091219e0cb1fe469c929fad6a725db678 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71562 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common/block/fast_spi: Hook up pci_dev_ops_pci to set SSIDKapil Porwal2023-01-041-0/+1
| | | | | | | | | | | | | | | | | | | | | BUG=none TEST=Verify presence of subsystem ID for fast_spi device on google/rex. lspci output before this patch: 00:1f.5 Serial bus controller [0c80]: Intel Corporation Device [8086:7e23] lspci output after this patch: 00:1f.5 Serial bus controller [0c80]: Intel Corporation Device [8086:7e23] Subsystem: Intel Corporation Device [8086:7e23] Note: UPD SiSkipSsidProgramming was set to 1 for above test. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I08c7a5a3fdc7389b315e85180c16d1ec335fbba2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/intel/common: Add API to check Key Locker supportPratikkumar Prajapati2023-01-043-2/+20
| | | | | | | | | | | | | Add is_keylocker_supported() API in common cpulib. This function checks if the CPU supports Key Locker feature. Returns true if Key Locker feature is supported otherwise false. Change-Id: Ide9e59a4f11a63df48838eab02c2c584cced12e1 Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71117 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/cezanne/psp_verstage/Makefile.inc: Remove path to non-existent ↵Elyes Haouas2023-01-031-1/+0
| | | | | | | | | | | | | | directories Found using 'Wmissing-include-dirs' command option. Fix: cc1: error: ../../src/soc/amd/cezanne/psp_verstage/include: No such file or directory [-Werror=missing-include-dirs] Change-Id: I36022a031cc08d2af8b982522b3d6652e679bf14 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* soc/amd/picasso/psp_verstage/Makefile.inc: Remove path to non-existent ↵Elyes Haouas2023-01-031-1/+0
| | | | | | | | | | | | | | directories Found using 'Wmissing-include-dirs' command option. Fix: cc1: error: ../../src/soc/amd/picasso/psp_verstage/include: No such file or directory [-Werror=missing-include-dirs] Change-Id: I7713eef54686c58a83215c461c3274cec89e32b0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* soc/amd/mendocino/psp_verstage/Makefile.inc: Remove path to non-existent ↵Elyes Haouas2023-01-031-1/+0
| | | | | | | | | | | | | | directory Found using 'Wmissing-include-dirs' command option. Fix: cc1: error: ../../src/soc/amd/mendocino/psp_verstage/include: No such file or directory [-Werror=missing-include-dirs] Change-Id: I1cc084abc7a9bfed760350f304dd074081a7eebf Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* soc/intel/baytrail: add _HRV to GPIO ACPI devicesMatt DeVillier2023-01-031-0/+6
| | | | | | | | | | | | | | | | For some reason, the Windows LPEA drivers won't attach without _HRV (hardware version) defined for the GPIO controllers. Add it, using value taken from Intel baytrail/valleyview edk2 reference code. TEST=boot Windows 10/11 on google/rambi, verify LPEA drivers load properly. Change-Id: Iaa6e1b3f68537e012e4a58175d5334a8aa2f4178 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/baytrail: add _HRV to I2C ACPI devicesMatt DeVillier2023-01-031-0/+14
| | | | | | | | | | | | | | | | For some reason, the Windows i2c drivers won't attach without _HRV (hardware version) defined for the i2c controllers. Add it, using value taken from Intel baytrail/valleyview edk2 reference code. TEST=boot Windows 10/11 on google/rambi, verify i2c drivers load properly. Change-Id: I590acd1f1b75f6bf2bf278e67eec1dcc24bcc15d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/common: Move SGX supported API to cpulibPratikkumar Prajapati2023-01-024-15/+16
| | | | | | | | | | | | | Move is_sgx_supported() API to common cpulib code, so that this function can be used by other code without enabling SOC_INTEL_COMMON_BLOCK_SGX_ENABLE config option. Change-Id: Ib630ac451152ae2471c862fced992dde3b49d05d Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-31 21:10:37 +0000