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* soc/intel/common/cpu: Remove the address-of (`&`) operator usageSubrata Banik2022-08-161-2/+2
| | | | | | | | | | | | | | | | | | | This patch drops explicit usage of the address-of operator ('&') while passing the function pointer (argument 0) to the `mp_run_on_all_cpus` API. Note: It's just cosmetic change without any real difference in the operation. TEST=Able to build and boot Google/Kano where CPU feature programming is successful on all logical processors. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I2c77959a76d2240ad1bfb7a9d7b9db7e8aee42f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66685 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* soc/amd/common/fsp/fsp-acpi: rework HOB pointer validity checkFelix Held2022-08-151-1/+1
| | | | | | | | | | | Checking if the return value of the fsp_find_extension_hob_by_guid call is NULL should make the code a bit easier to read. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6bdb07eab6da80f46c57f5d7b3c894b41ac23b8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66699 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/common/block/psp: Add psp_set_tpm_irq_gpioRaul E Rangel2022-08-154-0/+48
| | | | | | | | | | | | | | | | The PSP currently uses a hard coded GPIO for the TPM IRQ. Not all board versions use the same GPIO. This method allows the mainboard to pass in the correct GPIO. BUG=b:241824257 TEST=Boot guybrush and verify PSP message prints Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie05d095d7f141d6a526d08fbf25eb2652e96aa49 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* soc/amd/*: move reset_i2c_peripherals call after early GPIO setupFelix Held2022-08-154-8/+9
| | | | | | | | | | | | | | | | | | | | Since bootblock_soc_early_init gets called before bootblock_mainboard_early_init which does the early GPIO setup, external I2C level shifters that are controlled by GPIOs might not be enabled yet. Moving the reset_i2c_peripherals call to bootblock_soc_init makes sure that the early GPIO setup is already done when reset_i2c_peripherals is called. Haven't probed any SCL signal on the non-SoC side of the I2C level shifters yet, but the waveform on the SCL pin of I2C3 on the SoC of a barla/careena Chromebook doesn't have the longer than expected SCL pulses any more. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If02140aef56ed6db7ecee24811724b5b24e54a91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/intel/common/block/cse: Tidy up table in commentAngel Pons2022-08-141-3/+3
| | | | | | | | | | | | Adjust an ASCII art table so that it looks good: consistent padding and aligned table borders. Change-Id: I26196f969406e03f320256b0c3a337282f636914 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66707 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/qualcomm/sc7280: Add SocInfo support in corebootTaniya Das2022-08-143-0/+106
| | | | | | | | | | | | | | Add support for SocInfo in coreboot. The API socinfo_modem_supported is added to help to differentiate between LTE and WiFi SKUs. BUG=b:232302324 TEST=Validate boards are detected correctly on LTE and Wifi SKUs Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Change-Id: I61047ad49772c3796ba403cafde311ad184a4093 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
* Revert "soc/amd/sabrina: Re-init eSPI in bootblock"Karthikeyan Ramasubramanian2022-08-141-3/+3
| | | | | | | | | | | | | | | | | This reverts commit 8b1c6c6cb384c89659abbd043c2566df358d8f95. With updated APCB, eSPI configuration carries over to bootblock. Hence eSPI does not need to be re-initialized in bootblock. BUG=b:241426419 TEST=Build and boot to OS in Skyrim with PSP verstage. Cq-Depend: chrome-internal:4929421 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I426b07329d4a0154d915381c99dcc9746b7a3d7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* broadwell: Decouple LPDDR3 DQ/DQS maps from `pei_data`Angel Pons2022-08-143-0/+21
| | | | | | | | | | | | | Introduce the `BROADWELL_LPDDR3` Kconfig option along with some wrapper code to allow mainboards using LPDDR3 DRAM to supply the DQ/DQS maps to chipset code without having to use `pei_data`. The only mainboard using LPDDR3 is Google Samus. Change-Id: I0aaf0ace243c03600430c2a7ab6389a7b20cb432 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55812 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/broadwell: Consolidate SPD handlingAngel Pons2022-08-143-16/+35
| | | | | | | | | | | | | | | | | | | Mainboards do not need to know about `pei_data` to tell northbridge code where to find the SPD data. As done on Haswell, add the `mb_get_spd_map` function and the `struct spd_info` type to retrieve SPD information from mainboard code without having to use `pei_data` in said mainboard code. Unlike Haswell MRC, Broadwell MRC uses all positions of the `spd_data` array, not just the first. The placeholder SPD address for memory-down seems to be different as well. Adapt the existing code to handle these variations. Once complete, the abstraction layer for both MRC binaries will have the same API. Change-Id: I92a05003a319c354675368cae8e34980bd2f9e10 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* broadwell: Move some MRC/refcode settings to devicetreeAngel Pons2022-08-142-0/+10
| | | | | | | | | | | | | | | There's no generic way to tell whether a mainboard has an EC or not. Making Kconfig symbols for these options seems overkill, too. So, just put them on the devicetree. Also, drop unnecessary assignments when the board's current value is zero, as the struct defaults to zero already. Change-Id: I8d3b352333bea7ea6f7b0f96d73e6c2d7d1a2cfb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55809 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/google/auron: Move SPD file handling to chipsetAngel Pons2022-08-143-0/+100
| | | | | | | | | | | | The SPD file handling code is generic and can be used on any other mainboard. Move it to chipset scope to enable code reuse. Change-Id: I85b1460ccb82f0c1bf409db4a6b4c9355c25e76d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55808 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* broadwell: Compute channel disable masks at runtimeAngel Pons2022-08-142-0/+22
| | | | | | | | | | | | | Introduce the `SPD_MEMORY_DOWN` macro to indicate that a slot is used with memory-down. This enables computing the channel disable masks as the bits for slots where the SPD address is zero. To preserve current behavior, zero the SPD addresses for memory-down slots afterwards. Change-Id: I75b7be7c72062d1a26cfc7b09b79de62de0a9cea Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55807 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/mendocino/chipset_rembrandt: use right chipset folderFelix Held2022-08-131-1/+1
| | | | | | | | | | | | | Since the path after the chip keyword needs to point to the directory that contains the chipset's chip.h file, change this from soc/amd/rembrandt to soc/amd/mendocino. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I63334fbd59e74df491035b5cf7e296818cc02665 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66688 Reviewed-by: ritul guru <ritul.bits@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* src/mb: Update unlicensable files with the CC-PDDC SPDX IDMartin Roth2022-08-131-0/+2
| | | | | | | | | | | | | | | These files contain no creative content, and therefore have no copyright. This effectively means that they are in the public domain. This commit updates the unlicensable empty (and effectively empty) files with the CC-PDDX identifier for license compliance scanning. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I0b76921a32e482b6aed154dddaba368f29ac2207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66497 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8188: Initialize DFDRex-BC Chen2022-08-132-0/+12
| | | | | | | | | | | | | | | | | DFD (Design for Debug) is a debugging tool, which scans flip-flops and dumps to internal RAM on the WDT reset. After system reboots, those values can be shown for debugging using MTK internal parsing tools. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I6d19dc6f4e47ed69ba2ea87c79984020a413aee9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66586 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Move common definition of DFD to common folderRex-BC Chen2022-08-134-36/+4
| | | | | | | | | | | | | | | We use the same dump address and size for DFD in all MediaTek SoCs, so we move them to dfd_common.h and rename dfd_common.h to dfd.h. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I162bbb0a82e3b55c8cfbbd20e28a54ad01fd6b0d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66585 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8188: Fix the order of register address in addressmap.hRex-BC Chen2022-08-131-1/+1
| | | | | | | | | | | | TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ie9d7b361dda8c5850bc0682c255bc20f9e26675c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66668 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8188: Add tracker dumpRex-BC Chen2022-08-134-0/+15
| | | | | | | | | | | | | | | | | | | Tracker is a debugging tool. When bus timeout occurs, the system will reboot and latch some values of tracker registers which could be used for debugging. This function will be triggered only when it encounters the bus hanging issue. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I78f676c08ea44e9bb10bd99bbfed70e3e8ece993 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66584 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8188: replace SPDX identifiers to GPL-2.0-only OR MITMacpaul Lin2022-08-1335-35/+35
| | | | | | | | | | | | | | | | | | This replaces 'SPDX-License-Identifier' tags in all the files under soc/mediatek/mt8188 for better code re-use in other open source software stack. These files were originally from MediaTek and follow coreboot's main license: "GPL-2.0-only". Now MediaTek replaces these files to "GPL-2.0-only OR MIT" license. Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> Change-Id: If61e8b252400e8e5ecd185b6806b1ca279065f15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66628 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* Revert "soc/intel/alderlake: Enable energy efficiency turbo mode"Jeremy Compostella2022-08-131-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 844dcb3725fc95df53a7229703f5059d2c36f98e. A power and performance analysis performed on Alder Lake demonstrated that with an EPP (Energy Performance Preference) at 50% along with EET (Energy Efficient Turbo) disabled, the overall SoC performance are similar or better and the SoC uses less power. For instance some browser benchmark results improved by 2% and some multi-core tests by 4% while at the same time power consumption lowered by approximately 7.6%. BRANCH=firmware-brya-14505.B BUG=b:240669428 TEST=verify that ETT is disabled `iotools rdmsr 0 0x1fc' Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I96a72009aaf96d4237d57f4d5c8b1f41f87174d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66281 Reviewed-by: Zhixing Ma <zhixing.ma@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/amd/cezanne,common: factor out CPPC code to common AMD SoC codeFelix Held2022-08-127-3/+7
| | | | | | | | | | | | | | The Cezanne CPPC ACPI table generation code also applies to Sabrina, so move it to the common AMD SoC code directory so that it can be used for Sabrina too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5ce082a27429948f8af7f55944a1062ba03155da Reviewed-on: https://review.coreboot.org/c/coreboot/+/66400 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/mendocino: clear Port80 enable bit in ESPI DecodeJon Murphy2022-08-121-1/+0
| | | | | | | | | | | | | | | | | This reverts commit Ic152c295954d33ef1acddb3b06f0c6bbfbfb38ae. There was a bug that caused the SMU to hang when writing port80. it has since been resolved, so revert this workaround. BUG=b:227201571 TEST=Build and boot to OS in Skyrim. Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I5f10e282ab03756c7dbfb48182940f979eb122e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66470 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* soc/(amd|rockchip): Update vb2ex_hwcrypto implementations to new API reqJulius Werner2022-08-122-10/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | We want to extend the vb2ex_hwcrypto APIs on the vboot side to allow passing 0 for the data_size parameter to vb2ex_hwcrypto_digest_init() (see CL:3825558). This is because not all use cases allow knowing the amount of data to be hashed beforehand (most notable the metadata hash for CBFS verification), and some HW crypto engines do not need this information, so we don't want to preclude them from optimizing these use cases just because others do. The new API requirement is that data_size may be 0, which indicates that the amount of data to be hashed is unknown. If a HW crypto engine cannot support this case, it should return VB2_ERROR_EX_HWCRYPTO_UNSUPPORTED to those calls (this patch adds the code to do that to existing HW crypto implementations). If the passed-in data_size value is non-zero, the HW crypto implementation can trust that it is accurate. Also reduce a bit of the console spew for existing HW crypto implementations, since vboot already logs the same information anyway. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ieb7597080254b31ef2bdbc0defc91b119c618380 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* soc/mediatek/mt8186: Enable USB macro controlAllen-KH Cheng2022-08-124-2/+12
| | | | | | | | | | | | | | | | | | | When powering down SSUSB, the system needs to wait the ACK from SSUSB. We found that the setting of USB PAD top macro is not correct and it will cause timeout waiting for the ACK from SSUSB. To resolve this, we add mt_pll_set_usb_clock() in pll.c to enable usb macro control for powering down SSUSB. TEST=timeout of ssusb powerdown ack does not occur. BUG=b:239634625 Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.corp-partner.google.com> Change-Id: I58ba86e0467284e9947bfda1005c151a3e0c8881 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66600 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* Fix Alder Lake and Raptor Lake Device ID'sMaximilian Brune2022-08-122-87/+82
| | | | | | | | | | | | | | - ADP_P_* -> RPP_S_* (got mixed up I guess) - Remove duplicates of ADP_S_ESPI_* - Add infix _ESPI_ to all ADP_S device ID's Document: 619362 Change-Id: Ic18ecbd420fc598f0ef6e3cf38e987ac3ae6067e Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66629 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add missing ADL-S device identificationMaximilian Brune2022-08-122-0/+6
| | | | | | | | | | | | | | R680E, Q670E, H610E are the ADL-S IoT variants TEST=Boot ADL-S RVP DDR5 and see silicon info is reported as PCH: AlderLake-S R680E Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I1804994b4b72f0484eabb15323736679d2668078 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/meteorlake: Provide access to IOE through P2SB SBI for TCSSJohn Zhao2022-08-124-4/+22
| | | | | | | | | | | | | | | | | | | | This change provides access to IOE through P2SB Sideband interface for Meteor Lake TCSS functions of pad configuration and Thunderbolt authentication. There is a policy of locking the P2SB access at the end of platform initialization. The tbt_authentication is read from IOM register through IOE P2SB at early silicon initialization phase and its usage is deferred to usb4 driver. BUG=b:213574324 TEST=Built coreboot and validated booting to OS successfully on MTLRVP board. No boot hung was observed. Change-Id: Icd644c945bd293a8b9c4a364aaed99ec4a7c12f9 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66410 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
* soc/intel/common: Delete the TBT authenticaton functionJohn Zhao2022-08-121-5/+0
| | | | | | | | | | | | | | Delete the Thunderbolt authentication function ioe_tcss_valid_tbt_auth from the common block. Meteor Lake Platform will implement it. BUG=b:213574324 TEST=Built coreboot image successfully. Change-Id: I97a289faa6351fe562f91d8478b72c9403ce88cb Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
* soc/intel/alderlake: Fix DDR5 channel mappingAngel Pons2022-08-121-8/+6
| | | | | | | | | | | | | | | | | | | | | | | | | DDR5 memory modules have two separate 32-bit channels (40-bit on ECC memory modules), and the SPD info refers to one channel: the primary bus width is 32 (or 40) bits and the "DIMM size" is halved. On Alder Lake, there are 2 memory controllers with 4 32-bit channels each for DDR5. FSP has 16 positions to store SPD data, some of which are only used with LPDDR4/LPDDR5. To try to make things less confusing, FSP abstracts the DDR5 channels so that the configuration works like on DDR4. This is done by copying each DIMM's SPD data to the other half-channel. Thus, fix the wrapper parameters for DDR5 accordingly. Tested on AlderLake-P DDR5 RVP (board ID 0x12), both DIMM slots now function properly. Without this patch, only the top slot would work. Change-Id: I5f01cd77388b89ba34d91c2dc5fb843fe9db9826 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Tested-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66608 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/meteorlake: Have non prefetchable MMIO for IGD BAR0Wonkyu Kim2022-08-121-0/+1
| | | | | | | | | | | | | | Enable SOC_INTEL_GFX_NON_PREFETCHABLE_MMIO for MTL to fix guc driver failure. BUG=b:241746156 TEST=boot to OS and check guc driver loading successful Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ifc20935bccdda55db3e57eecd37a4260b3f1a2d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66613 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common: Ignore prefetch PCI attribute for IGD BAR0Wonkyu Kim2022-08-122-1/+19
| | | | | | | | | | | | | | | | | | | | | | | | From Meteorlake, IGD BAR0(GTTMMADR) is changed to 64bit prefetchable. Due to the prefetchable attribute, resource allocation for IGD BAR0 is assigned WC memory and it causes kernel driver failure. For avoiding kernel driver failure, ignore prefetch PCI attribute for IGD BAR0 to assign UC memory. We're working on publishing below information. - IGD BAR0(GTTMMADR) is changed to 64bit prefetchable BAR - GTTMMADDR BAR should be always mapped as UC memory although marked Pre-fetchable. BUG=b:241746156 TEST=boot to OS and check guc driver loading successful Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I76d816d51f32f99c5ebcca54f13ec6d4ba77bba5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66403 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
* treewide: Rename Sabrina to MendocinoJon Murphy2022-08-1167-132/+132
| | | | | | | | | | | | | | | | | | | | | 'Mendocino' was an embargoed name and could previously not be used in references to Skyrim. coreboot has references to sabrina both in directory structure and in files. This will make life difficult for people looking for Mendocino support in the long term. The code name should be replaced with "mendocino". BUG=b:239072117 TEST=Builds Cq-Depend: chromium:3764023 Cq-Depend: chromium:3763392 Cq-Depend: chrome-internal:4876777 Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I2d0f76fde07a209a79f7e1596cc8064e53f06ada Reviewed-on: https://review.coreboot.org/c/coreboot/+/65861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* src/mb: Add SPDX identifiers to files missing themMartin Roth2022-08-111-0/+2
| | | | | | | | | | | | | This adds SPDX identifiers to the remaining source files in the mainboard directory that don't already have them. Change-Id: I1adc204624f3ab6fcafd8fbb239e6d69e057973a Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66498 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* src/soc/intel/mtl: Add VPU supportSrinidhi N Kaushik2022-08-112-0/+5
| | | | | | | | | | | | | | This change adds support for enabling VPU on MTL SoC. BUG=b:240665069 TEST=build coreboot mtlrvp Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ie79b45f34a669b9ff777599cb85217abac6cb74e Reviewed-on: https://review.coreboot.org/c/coreboot/+/66566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
* soc/intel/tigerlake: Add USBOTG and CrashLog to irq tableFrans Hendriks2022-08-102-0/+3
| | | | | | | | | | | | | | | FSP reports missing IRQ for devices. Add USBOTG (D20:F1) and CrashLog & Telemetry (D10:F0) to irq_constrain. Bug = N/A TEST = Build and boot Siemens AS-TGL1 Change-Id: Ic02d33045a07a6888ba97d8f2c6fa71bc7e363e8 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/{zork,guybrush,skyrim},soc/amd/espi: Fix vw_irq_polarityRaul E Rangel2022-08-101-7/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The default state for the IRQ lines when the eSPI controller comes out of reset is high. This is because the IRQ lines are shared with the other IRQ sources using AND gates. This means that in order to not cause any spurious interrupts or miss any interrupts, the IO-APIC must use a low polarity trigger. On zork/guybrush/skyrim the eSPI IRQs are currently working as follows: * On power on/resume the eSPI controller drives IRQ 1 high. * eSPI controller gets configured to not invert IRQ 1. * OS configures IO-APIC IRQ 1 as Edge/High. * EC writes to HIKDO (Keyboard Data Out) which causes the EC to set IRQ1 high. * eSPI controller receives IRQ 1 high, doesn't invert it, and leaves IRQ 1 as high. This results in missing the first interrupt. * When the x86 reads from HIKDO, the EC deasserts IRQ1. This causes the eSPI controller to set IRQ1 to low. We are now primed to catch the next edge high interrupt. This is generally not a problem since the linux driver will probe the 8042 with interrupts off. On S3/S0i3 resume since the eSPI controller comes out of reset driving the IRQ lines high, we trigger a spurious IRQ since the IO-APIC is configured to trigger on edge high. This results in the 8042 controller getting incorrectly marked as a wake trigger. By configuring the IO-APIC to use low polarity interrupts, we no longer lose the first interrupt. This also means we can use a level interrupt to match what the EC actually asserts. We use the `Interrupt` keyword instead of the `IRQ` keyword in the ACPI because the linux kernel will ignore the level/polarity parameters for the `IRQ` keyword and default to `edge/high. `Interrupt` doesn't have this problem. The PIC is not currently configured anywhere and it defaults to an edge/high trigger. We could add some code to configure the PICs trigger register, but I don't think we need the functionality right now. For zork and guybrush, this change is a no-op. eSPI is configured in verstage which is located in RO, and we have already locked RO for these devices. We will need to figure out how to properly set the `vw_irq_polarity` for these devices. BUG=b:218874489, b:160595155, b:184752352, b:157984427, b:238818104 TEST=On zork, guybrush and skyrim $ suspend_stress_test --post_resume_command 'cat /sys/devices/platform/i8042/serio0/wakeup/wakeup35/active_count' Verify keyboard works as expected and no interrupt storms are observed. On morphius I verified keyboard and mouse work on windows as well. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4608a7684e34ebb389e0e55ceba7e7441939afe7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* soc/amd/sabrina: Rename PSP SPL defaultMarshall Dawson2022-08-081-1/+1
| | | | | | | | | | | | | | | | Change the SPL file from the 'cezanne' placeholder to a mendocino filename. Also, move the default location to blobs/mainboard since it's not board-agnostic. BUG=b:241543152 BUILD=Enable feature and build amd/chausie Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I47647c5d926484e25e3f893e72c671554e277a56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* soc/amd/sabrina: Rename PSP whitelist defaultMarshall Dawson2022-08-081-1/+1
| | | | | | | | | | | | | Change the name of the whitelist file from the 'cezanne' placeholder to a mendocino path/to/file. Also, as whitelist files won't be pushed into a public repo, modify the path to point to site-local. Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I49bbf1335606567735e36ed9bda1314bfc6247d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/sabrina: Use new mendocino amd_blobsMarshall Dawson2022-08-071-32/+32
| | | | | | | | | | | | | | | | | | Modify sabrina's fw.cfg to point to the proper directory and use the standard names, as released by AMD. The name 'sabrina' was an alias used for the Mendocino product. The public-facing builds have been using Cezanne blobs, renamed as Sabrina or SBR, but can now take advantage of the appropriate blobs. BUG=b:239072117 TEST=Build amd/chausie Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: Id646844e41980802be1e39dce96e5adaace4311d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/intel/alderlake: Fix RPL-P 282 15W GT ICC MAXJeremy Compostella2022-08-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | The software used to read the document listing the VR settings turns out to not be perfectly compatible. Indeed, it displays a value of 55A for RPL-P 282 15W GT ICC MAX while the correct value actually is 40A. After a thorough review using the software used to create the document, it is the only value presenting a discrepancy. BRANCH=firmware-brya-14505.B BUG=b:239797178 TEST=build and boot Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: Iee293c87a66f0cd32714766e3ad81eee1a411723 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66057 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* soc/amd/sabrina: Enable PSP Crypto Co-Processor (CCP) DMAKarthikeyan Ramasubramanian2022-08-071-1/+1
| | | | | | | | | | | | | | | | Boot issue while using FW slot A has been root-caused to the usage of same TLB to map HW Crypto engines and SPI flash. With upcoming PSP release, this TLB usage conflict has been resolved. Hence enable CCP DMA. BUG=b:240175446 TEST=Build and boot to OS in Skyrim with PSP verstage using CCP DMA. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I2b12adb7e94e489bf07963a6f9a829cf4b36ad5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/sabrina: Re-init eSPI in bootblockKarthikeyan Ramasubramanian2022-08-071-3/+3
| | | | | | | | | | | | | | | | Currently bootblock does not initialize eSPI if it is already done in PSP verstage. But some other component is clobbering the eSPI configuration causing timeouts in EC communication after the boot flow hits x86. To workaround this issue, re-initialize eSPI in bootblock. BUG=b:217414563 TEST=Build and boot to OS in Skyrim with PSP verstage. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I41c0b2816a106a6a547f3cb372693e1bb7f23734 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/intel/tigerlake: Expose In-Band ECC config to mainboardFrans Hendriks2022-08-072-0/+37
| | | | | | | | | | | | | | | | Support for feature "In-Band ECC" not available for Tiger Lake Similar to Elkhart Lake, Tiger Lake also provides this feature. Ported from Elkhart Lake (CB:55668) Bug = N/A TEST = Build and boot Siemens AS-TGL1 Change-Id: Ie54d5f6a9747fad0105d0f8bf725be611bb8cf60 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/mtl: Remove deprecated FSP optionSrinidhi N Kaushik2022-08-051-1/+0
| | | | | | | | | | | | | | | Remove the reference to `CpuCrashLogDevice` UPD since FSP v2304.01 has deprecated this UPD. BUG=b:240665069 TEST=build rex coreboot Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I23223fd7936a60d974229b553de255a7dcf4416b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66357 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/amd/cezanne/cppc: drop duplicate newlineFelix Held2022-08-041-1/+0
| | | | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I774be6d80e0aae725ecb1027501c8d66e0bf5a08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* soc/amd/cezanne/cppc: reduce visibility of cpu_init_cppc_configFelix Held2022-08-042-2/+1
| | | | | | | | | | | | | This function is only called from the same compilation unit, so turn it into a static function. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5c2deaa46f69c763df9612e39415b37c60d631be Reviewed-on: https://review.coreboot.org/c/coreboot/+/66398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* soc/mediatek: Move common definitions to dramc_soc_common.hRex-BC Chen2022-08-034-48/+28
| | | | | | | | | | | | | | Some definitions are the same in dramc_soc.h for MT8192, MT8195 and MT8186, so we move them to dramc_soc_common.h TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I3095333e62abf98de1f2d27033baeeba7a4cad79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66276 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Add config for IoT FSP supportLean Sheng Tan2022-08-031-0/+10
| | | | | | | | | | | | | Add new config FSP_TYPE_IOT to add the IoT FSP option so that respective mainboard Kconfig can use IoT FSP if needed. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I01d891348c039269138e64290ae3d6ec75d3c687 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66367 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/soc/intel: Add UFS device with ref-clk-freq propertyMeera Ravindranath2022-08-034-0/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | UFS storage devices require the bRefClkFreq attribute to be set to operate correctly in high speed mode. The correct value is determined by what the SoC / board supports. For the ADL UFS controller, it is 19.2 MHz. a) Introduce a new ACPI property "ref-clk-freq". b) Add support to configure this property using an SoC Kconfig. Kernel patch: https://web.archive.org/web/20220801060732/https://lore.kernel.org/all/ 20220715210230.1.I365d113d275117dee8fd055ce4fc7e6aebd0bce9@changeid/ BUG=b:238262674 TEST=Build,boot Nirwen and dump SSDT entries and check that the kernel correctly parses ref-clk-freq as 19.2 MHz. Scope (\_SB.PCI0) { Device (UFS) { Name (_ADR, 0x0000000000120007) // _ADR: Address Name (_DDN, "UFS Controller") // _DDN: DOS Device Name Name (_DSD, Package (0x02) // _DSD: Device-Specific Data { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") /* Device Properties for _DSD */, Package (0x01) { Package (0x02) { "ref-clk-freq", 0x0124F800 } } }) } } Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Signed-off-by: Reka Norman <rekanorman@chromium.org> Change-Id: I80c338a8a61f161b0feb6c5a3ca00cf5e0cfb36c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* soc/amd/sabrina/fch: enable XTAL pad disabling in S0i3Felix Held2022-08-032-0/+2
| | | | | | | | | | | | | | | | | | Switching off the pads of the internal crystal oscillator that connect to the crystal on the board in S0i3 saves a little power, so enable it. No measurements to quantify the power savings have been made. PPR #57243 revision 1.59 was used as a reference. BUG=b:237647468 TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I52f14ae5c614ad8ff0479b619de7164afa1e7648 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66336 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-03 00:07:54 +0000