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* soc/intel/cannonlake: Set platform Debug Probe TypeLijian Zhao2017-10-182-0/+11
* soc/intel/cannonlake: Update PCIE CLKREQ programingLijian Zhao2017-10-184-4/+36
* soc/intel/cannonlake: Add finalize functionLijian Zhao2017-10-184-0/+263
* soc/intel/cannonlake: Calculate soc reserved memory sizeSubrata Banik2017-10-181-0/+15
* soc/intel/cannonlake: Use EBDA area to store cbmem_top addressSubrata Banik2017-10-185-49/+76
* soc/intel/cannonlake: Refactor memory layout calculationSubrata Banik2017-10-181-48/+119
* soc/intel/cannonlake: Create acpi_get_sleep_type() to get previous sleep stateSubrata Banik2017-10-181-2/+8
* soc/amd/stoneyridge: clean up chip.hMartin Roth2017-10-171-6/+0
* soc/intel/common/block/pmc: Move pmc_disable_all_gpe to romstageFurquan Shaikh2017-10-172-3/+15
* soc/intel/common: sanity check ebda signatureAaron Durbin2017-10-163-2/+15
* console/flashconsole: Enable support for postcarYouness Alaoui2017-10-162-0/+3
* src/soc/skylake: Fix Null pointer dereferencesShaunak Saha2017-10-161-0/+1
* intel/common: CAR setup CQOSNaresh G Solanki2017-10-161-3/+28
* soc/amd/common: Clean up file includesFrank Vibrans2017-10-161-2/+0
* soc/amd/stoneyridge: Check UART indexMarshall Dawson2017-10-163-0/+11
* soc/amd/stoneyridge: Update AMD firmware placement optionsMartin Roth2017-10-162-10/+18
* amd/stoneyridge: Add function to find PmControl registerMarshall Dawson2017-10-152-0/+6
* amd/soc/common: Print an error if an AGESA callout isn't supportedMarc Jones2017-10-151-1/+5
* soc/amd/stoneyridge/lpc.c: Refactor lpc_enable_childrens_resourcesRichard Spiegel2017-10-151-114/+137
* intel/skylake: Use Sata related registers from devicetreeYouness Alaoui2017-10-141-1/+4
* amd/stoneyridge: Make all AGESA reset requests immediateMarc Jones2017-10-131-7/+4
* intel/common/pmc: Disable all GPEs during pmc_initFurquan Shaikh2017-10-121-0/+2
* soc/intel/common: Clean up PMC library GPE handling APIFurquan Shaikh2017-10-1211-71/+80
* soc/intel/cannonlake: add length information for communitiesBora Guvendik2017-10-121-0/+6
* soc/intel/cannonlake: Add ACPI platform sleep capabilityVaibhav Shankar2017-10-121-0/+20
* soc/amd/stoneyridge: Clean up sata.cRichard Spiegel2017-10-121-4/+2
* intel/fsp_broadwell_de: Add timestamp functionalityWerner Zeh2017-10-123-0/+34
* soc/intel/skylake: Enable bus master for sataKane Chen2017-10-121-0/+5
* soc/intel/cannonlake: Change default UART number to 2Lijian Zhao2017-10-111-1/+1
* soc/intel/skylake: Fix broken suspend/resume for deep S3Furquan Shaikh2017-10-101-1/+2
* soc/intel/*lake: Load vbt when it's neededPatrick Georgi2017-10-092-12/+2
* soc/intel/skylake: use locate_vbt directly instead of calling a wrapperPatrick Georgi2017-10-061-2/+3
* soc/intel/common: refactor locate_vbt and vbt_getPatrick Georgi2017-10-065-26/+27
* soc/intel/common: refactor locate_vbtPatrick Georgi2017-10-063-20/+8
* soc/intel/common: Allow overriding CBFS filename of VBTPatrick Georgi2017-10-062-1/+17
* soc/intel/cannonlake: Enable MRC cacheLijian Zhao2017-10-061-0/+2
* soc/intel/cannonlake: reduce bootblock sizeAaron Durbin2017-10-061-0/+4
* soc/intel/common: remove invalid path from Kconfig includeAaron Durbin2017-10-061-1/+0
* soc/intel/cannonlake: Add all the SOC level DSDT tablesLijian Zhao2017-10-058-0/+635
* soc/intel/skylake: Add support in SKL for PMC common codeShaunak Saha2017-10-0513-548/+133
* soc/intel/common/block: Manage power state variable from common PMC blockShaunak Saha2017-10-052-1/+38
* soc/amd/stoneyridge: Pass firmware dir location to amdfwtoolMartin Roth2017-10-051-0/+1
* soc/intel/{common,apollolake}: Add checks to handle negative valuesRizwan Qureshi2017-10-052-2/+8
* soc/intel/skylake: Add config for mbx command for Intersil VR C-state issuesRizwan Qureshi2017-10-052-0/+16
* vendor/intel/skykabylake: Update FSP header files to version 2.7.2Balaji Manigandan B2017-10-051-4/+4
* chromeec: Remove checks for EC in RODaisuke Nojiri2017-10-043-17/+0
* soc/amd/stoneyridge: Drop some amdlib.h includesKyösti Mälkki2017-10-043-3/+0
* soc/intel/cannonlake: change gpio device nameBora Guvendik2017-10-031-1/+1
* soc/intel/cannonlake: Disable CPU ratio overrideLijian Zhao2017-10-031-0/+2
* soc/intel/cannonlake: add initial ASL methods for SCS, GPIOBora Guvendik2017-10-035-0/+160
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