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* i945: Consolidate FADT codeclassic-2014.10Vladimir Serbinenko2014-10-182-0/+110
| | | | | | | | Change-Id: I076cba7d21926cabf90d485de50268ae40c435f3 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7087 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* lenovo/t520: Use native raminit over MRC blobNicolas Reinecke2014-10-171-1/+1
| | | | | | | | | | | | | | | Native raminit for sandy/ivybridge was introduced in: 7686a56 sandy/ivybridge: Native raminit. An additional current level is needed. Change-Id: Ied73d168045c25d37afa5d9d7073de7f9c6435c7 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: http://review.coreboot.org/7098 Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Tested-by: build bot (Jenkins)
* Fix ICH spi implementation which reads data from different chips.Philipp Deppenwiese2014-10-171-3/+3
| | | | | | | | | | | | | | This patch adjusts the read timeout in order to support flash chips which needs more than 60ms to complete a spi command. This problem can be reproduced on a Thinkpad T520 with M25PX64 spi chip ( suspend to ram bug ). Change-Id: I22b2e59f1855ead6162a292b83b9b854b55c0235 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: http://review.coreboot.org/7105 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
* bd82x6x: Consolidate common GNVS initVladimir Serbinenko2014-10-171-0/+9
| | | | | | | | Change-Id: Iea035f80695623e4e8d53eea7e3ec294d868fb5b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7053 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* bd82x6x: Consolidate early native USB initVladimir Serbinenko2014-10-173-5/+93
| | | | | | | | Change-Id: I6189930fd3c69c3497e4cf1a78035e6614761b13 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6923 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* bd82x6x: Move common bd82x6x S3 detect to bd82x6x code.Vladimir Serbinenko2014-10-162-0/+32
| | | | | | | | Change-Id: I9ba1fa5f9ad38cb619466c6199eacd219bc53281 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6921 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* ACPI: Remove CONFIG_GENERATE_ACPI_TABLESVladimir Serbinenko2014-10-162-3/+3
| | | | | | | | | | | As currently many systems would be barely functional without ACPI, always generate ACPI tables if supported. Change-Id: I372dbd03101030c904dab153552a1291f3b63518 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4609 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
* i945: Convert to per-device ACPIVladimir Serbinenko2014-10-153-2/+28
| | | | | | | | Change-Id: Iee3ee33ca58b8c722d2d38aae31e7130032512ad Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6804 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
* gm45: Convert to per-device ACPIVladimir Serbinenko2014-10-154-1/+36
| | | | | | | | Change-Id: Ib04b03b2dc2ad3bfa886b43df9dd6518bbb46e3f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6803 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
* bd82x6x, ibexpeak, lynxpoint: Declare NVSA before its use.Vladimir Serbinenko2014-10-113-14/+8
| | | | | | | | | | Windows chokes if it's not the case. Change-Id: I3df15228ed00c3124b8d42fc01d7d63ff3fe07ba Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7017 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
* lynxpoint: Change OEM table ID for serialio.Vladimir Serbinenko2014-10-101-2/+2
| | | | | | | | | | | According to ACPI spec all SSDTs should have distinct OEM table ID. We end up with 2 SSDTs named "COREBOOT". Fix this. Change-Id: I01bccb72758baf51c6b4263778716f4bb9d438c9 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7016 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
* bd82x6x, ibexpeak, lynxpoint: Ensure 0-filling of uninited GNVS vars.Vladimir Serbinenko2014-10-103-1/+16
| | | | | | | | Change-Id: I672c3ca9e7f30a21330cf1920a25b1ab38b3f282 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7015 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
* haswell: Move to per-device ACPIVladimir Serbinenko2014-09-223-2/+65
| | | | | | | | Change-Id: Ic724dcf516d9cb78e89698da603151a32d24e978 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6814 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
* lynxpoint: Don't enable SMI handling of TCODuncan Laurie2014-09-181-2/+2
| | | | | | | | | | | | | | | We have no good reason to be handling the TCO timeout as an SMI since we aren't doing anything special with it and clearing the status in the handler prevents the reboot from actually happening. Change-Id: I074ac0cfa7230606690e3f0e4c40ebc2a8713635 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180672 (cherry picked from commit 608a2c5768e9300c81b7c72fb8ab7a0c7c142bec) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6907 Tested-by: build bot (Jenkins)
* southbridge/bd82x6x: Reserve 16 MiB for flash and not 8.Vladimir Serbinenko2014-09-131-2/+5
| | | | | | | | | | | X230 has 12 MiB flash. SPI controller supports up to 2 x 16 MiB of flash but address map limits this to 16MiB. Change-Id: Icc39c3c8d45d2d14e437bdfce920f8b4b039789d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5133 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* azalia: Shrink boilerplateVladimir Serbinenko2014-09-1310-24/+16
| | | | | | | | | Change-Id: Ib3e09644c0ee71aacb067adaa85653d151b52078 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6840 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* sch: make separate copy of nvs.hVladimir Serbinenko2014-09-121-0/+137
| | | | | | | | Change-Id: Ie3a843a76ebf9f5d825e14c4359fb3ecaa052e38 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6809 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Move nehalem/sandy/ivy to per-device acpiVladimir Serbinenko2014-09-117-2/+68
| | | | | | | | Change-Id: I3d664ab575bf9c49a7bff9a395fbab96748430d0 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6802 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
* i82801gx: Kill unused TCG and SMI1Vladimir Serbinenko2014-09-052-19/+2
| | | | | | | | | | | SMI1 is being written to but never read from. Change-Id: I82c0800713e3093eb1317b5e1f6f228771134857 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6808 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* sandybridge: Add native sandybridgeVladimir Serbinenko2014-08-302-2/+3
| | | | | | | | Change-Id: I1b51310b4387e588c4828563620b0e2770598503 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6753 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* southbridge/intel/fsp_rangeley: fix to include irqroute.h twiceMartin Roth2014-08-181-0/+6
| | | | | | | | | | | | | | | | This matches what was done on baytrail in commit bfca984b - soc/intel/fsp_baytrail: set up for including irqroute.h twice irq_helper.h intentionally gets included into irqroute.asl twice - once for pic mode and once for apic mode. Since people are used to seeing guard statements on the .h files, add the guards to irqroute.h and add a comment to irq_helper.h explaining why they aren't there. Change-Id: I709f9370ce7db1b3ffac2297aeaba5cc670ec20c Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6606 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* gm45: Move S3 detection to enable stage.Vladimir Serbinenko2014-08-121-17/+0
| | | | | | | | | | Also move it to NB to be in line with other. Change-Id: Ibd961d60dcd686899f34f6a494c14ff9d65e618b Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6625 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* i82801ix: Make RP04 optionally hotpluggable.Vladimir Serbinenko2014-08-122-6/+53
| | | | | | | | Change-Id: I34a1ae4bff22db6ee55fa511de39bdfd5dd92c7e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6627 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* i82801ix: Declare gen decode registers.Vladimir Serbinenko2014-08-111-0/+3
| | | | | | | | Change-Id: I999818833c9040eb4f4e19c313b5e9be216ffd86 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6585 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* lynxpoint: Add interrupt for GPIO controller in ACPI deviceDuncan Laurie2014-08-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | The GPIO controller uses IRQ14 as an active high level triggered source for GPIOs that are configured to trigger shared interrupt. This was also tested on bolt by configuring the touchscreen to use a shared GPIO interrupt: localhost ~ $ grep atmel_mxt_ts /proc/interrupts 54: 24 188 93 124 LP-GPIO-demux atmel_mxt_ts Change-Id: I3765120112bae11407e5b2020399d0d0b8e3cef8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171901 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 63a0c80ce5a19410d0608fede5a9fe0ec1c8e5c1) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6541 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* intel/fsp_bd82x6x: Fix cycle error some morePatrick Georgi2014-08-101-1/+1
| | | | | | | | | | | | | As a follow up to #6479 (63e1948643fcbd763c83b6baa6cd9a077d49f1fc), fix the remaining faulty loop. Change-Id: I2c77efe620c71e939f4d74e48f90a166c782e5f5 Found-by: Coverity Scan Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6569 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* intel/fsp_bd82x6x: Fix cycle errorPatrick Georgi2014-08-032-2/+2
| | | | | | | | | | | | | Some copy-pasta snuck in that reintroduced an error already fixed in #3435 (62f8083dfdf0c5e0046efe297b2bf88474928071) Change-Id: I47db23e88fa09c73b4cf3e99fe2d0ed2ac30fd80 Found-by: Coverity Scan Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6479 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* i82801ix: Provide ramstage smbus functions.Vladimir Serbinenko2014-08-013-0/+162
| | | | | | | | Change-Id: Idc62e382a4002274abe6c23d76fe0874c62846c5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6433 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* southbridge/intel: Add fsp_rangeley supportMartin Roth2014-07-3038-0/+5707
| | | | | | | | | | | | | This adds the southbridge initialization pieces for Intel's Atom C2000 processor (formerly Rangeley). It is intended to be used with the Intel Atom C2000 FSP and does not contain all of the pieces that would otherwise be required for initialization. Change-Id: I416e85bd6e9c9dcf79f97785074135902fdd18b7 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/6370 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* i82801ix: Allow configuration of SATA mode in CMOS.Vladimir Serbinenko2014-07-302-9/+16
| | | | | | | | | Change-Id: Ice0f0273b16a946143c038a90b61978269c1c56e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6409 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* i82801ix: Enable usbdebug options.Vladimir Serbinenko2014-07-301-0/+1
| | | | | | | | | | Needed to be able to choose convenient usbdebug port. Change-Id: I84b304f0f8fa79cc8d4a136ee6d78dc7659601c9 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6410 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* sandy/ivybridge: Native raminit (lint clean)Edward O'Callaghan2014-07-291-4/+4
| | | | | | | | | | | | | Remove some trailing whitespaces and add header guards for code introduced in: 7686a56 sandy/ivybridge: Native raminit Change-Id: Ifc9a785ea3a43cfe1f406b57eeba9b5f94f36711 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6393 Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Tested-by: build bot (Jenkins)
* sandy/ivybridge: Native raminit.Vladimir Serbinenko2014-07-297-4/+757
| | | | | | | | | | | | | | Based on damo22's work and my X230 tracing. Works for my X230 in a variety of RAM configs. Also-By: Damien Zammit <damien@zamaudio.com> Change-Id: I1aa024c55a8416fc53b25e7123037df0e55a2769 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/5786 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* intel/lynxpoint/Kconfig: Remove duplicate option `IFD_BIN_PATH`Paul Menzel2014-07-171-4/+0
| | | | | | | | | | | | | | | | | | Currently `IFD_BIN_PATH` is shown twice. Commit 5218e616 (intel/lynxpoint: Allow building without IFD (descripter.bin)) [1] accidentally added the option another time. So fix up the commit and remove one of the two options `IFD_BIN_PATH`. Keep the one which depends on `!HAVE_IFD_BIN` and is around the IFD options. [1] http://review.coreboot.org/6046 Change-Id: Id46f01ab8ee2e752e337e687a2ef0dfa374f44a5 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6269 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>
* southbridge,Makefile.inc: Trivial - drop trailing blank lines at EOFEdward O'Callaghan2014-07-172-2/+0
| | | | | | | | Change-Id: Ied03e8814ea13f0e677a1d34da19efe6dfebf72f Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6288 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
* southbridge,ASL: Trivial - drop trailing blank lines at EOFEdward O'Callaghan2014-07-1746-55/+0
| | | | | | | | Change-Id: I8ef5f1571ad14ead2d4cc0d61b6b7133d7fc8550 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6293 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
* southbridge/intel/bd82x6x/me_8.x.c: Trivial - space to tab fixEdward O'Callaghan2014-07-151-4/+3
| | | | | | | | Change-Id: I5b6d0a1f5f96a8d6cfc5a14baaa0f9267339b072 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6268 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* SPI: Split writes using spi_crop_chunk()Kyösti Mälkki2014-07-141-1/+6
| | | | | | | | | | | SPI controllers in Intel and AMD bridges have a slightly different restriction on how long transactions they can handle. Change-Id: I3d149d4b7e7e9633482a153d5e380a86c553d871 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6163 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* libpayload: find source of input charactersLuigi Semenzato2014-07-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | This change makes it possible for vboot to avoid an exploit that could cause involuntary switch to dev mode. It gives depthcharge/vboot some information on the type of input device that generated a key. BUG=chrome-os-partner:21729 TEST=manually tested for panther BRANCH=none CQ-DEPEND=CL:182420,CL:182241,CL:182946 Change-Id: I87bdac34bfc50f3adb0b35a2c57a8f95f4fbc35b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://chromium-review.googlesource.com/182357 Reviewed-by: Luigi Semenzato <semenzato@chromium.org> Tested-by: Luigi Semenzato <semenzato@chromium.org> Commit-Queue: Luigi Semenzato <semenzato@chromium.org> Reviewed-on: http://review.coreboot.org/6003 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* intel/lynxpoint: Allow to always route USB3 ports to XHCIStefan Reinauer2014-07-112-0/+9
| | | | | | | | | | | | | | | | | | | | | This will make USB keyboards connected to USB3 ports work in libpayload on Beltino. BUG=chrome-os-partner:23396 BRANCH=none TEST=Use USB keyboard on Beltino in dev mode screen Change-Id: I70b03d733bd9e4c8be5673b48bd2196effa8a5e7 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/173640 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> [pm: rebase to master branch of coreboot upstream] Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6018 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* intel/lynxpoint: Work around XHCI resume issuesDuncan Laurie2014-07-111-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When USB3 devices are attached while in suspend, or two USB3 devices that are both plugged in are switched to the other port while in suspend the kernel does not seem to notice this -- despite the cold attach status bit. This results in the devices showing up in the USB list at the old enumerated device numbers and higher layers continuing to think they are present but not reseponding. With the kernel workaround to deal with devices that are logically disconnected it is possible for firmware to send a warm port reset to devices that are in this state and then the kernel will see them disappear and handle it properly. This same issue exists in the EFI firmware on the Whitetip Mountain 2 reference board so it is not specifically a coreboot bug. If this behavior is fixed in the kernel then this workaround could be removed since it is in RW firmware. BUG=chrome-os-partner:22818 BRANCH=falco,peppy,wolf,leon TEST=manual: 1) attach two USB3 devices 2) suspend system 3) switch the ports that the USB3 devices are attatched to 4) resume system 5) confirm that the devices are re-enumerated and come up properly Original-Change-Id: Ifba3ffc94a06dc0b2436d7d7d464d824657362af Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170335 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 203d200268f4af6445224962190cbc66ad2a83e4) Change-Id: I54fd2847ee25a60f25c2cefebdc1a3c18455464a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170579 [pm: rebase to master branch of coreboot upstream] Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6017 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* intel/lynxpoint: xhci: Revert suspend/resume changesDuncan Laurie2014-07-111-85/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I have been attempting to work around USB3 issues that appear in the kernel with hacks in the firmware, but this is resulting in more headaches in the kernel. Instead remove all the work that was being done at resume time and undo the change that was issuing a warm reset to all ports at suspend time. The bad device behavior will be dealt with at the kernel level to handle devices that get stuck in polling state after enable/disable sequence. BUG=chrome-os-partner:22754 BRANCH=falco,peppy,wolf,leon TEST=manual: suspend/resume with several misbehaving devices: Kingston USB3 Media Reader Transcend USB3 Media Reader Various ADATA USB3 drives Various Kingston USB3 sticks Original-Change-Id: I0894454af42d2ced456fe0da921d74c9e74902d0 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170107 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit c2abb4d0dad6ed00e1e230d604c4c0a76eb4eef7) Change-Id: Ib215d9c230f90a1c9f34bf29254bb9feec28c67e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170578 [pm: rebase to master branch of coreboot upstream] Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6016 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* southbridge: Trivial - drop trailing blank lines at EOFEdward O'Callaghan2014-07-0863-69/+0
| | | | | | | | Change-Id: I5484ebb665453777cc3b2561be6e50c787f1a257 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6209 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* spi: Change spi_xfer to work in units of bytes instead of bits.Gabe Black2014-07-051-10/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Whenever spi_xfer is called and whenver it's implemented, the natural unit for the amount of data being transfered is bytes. The API expected things to be expressed in bits, however, which led to a lot of multiplying and dividing by eight, and checkes to make sure things were multiples of eight. All of that can now be removed. BUG=None TEST=Built and booted on link, falco, peach_pit and nyan and looked for SPI errors in the firmware log. Built for rambi. BRANCH=None Change-Id: I02365bdb6960a35def7be7a0cd1aa0a2cc09392f Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/192049 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> [km: cherry-pick from chromium] Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6175 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* spi: Remove unused parameters from spi_flash_probe and setup_spi_slave.Gabe Black2014-07-051-2/+1
| | | | | | | | | | | | | | | | | | | | | | | The spi_flash_probe and and spi_setup_slave functions each took a max_hz parameter and a spi_mode parameter which were never used. BUG=None TEST=Built for link, falco, rambi, nyan. BRANCH=None Change-Id: I3a2e0a9ab530bcc0f722f81f00e8c7bd1f6d2a22 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/192046 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> [km: cherry-pick from chromium] Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6174 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* intel/lynxpoint: Build intermediate step to add Lynx Point ME imageDuncan Laurie2014-07-051-2/+1
| | | | | | | | | | | | | | | | | This is needed to successfully build fox_wtm2 from external repo. BUG=chrome-os-partner:18638 BRANCH=none TEST=manual: successfully compile coreboot for fox_wtm2 and create an image with chromeos-bootimage/cros_bundle_firmware Change-Id: Iaa4e9983faa1d86c2b29d8fd4f577be035497e38 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/48676 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4132 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* intel/lynxpoint: xhci: Port reset changes on suspend/resumeDuncan Laurie2014-07-051-17/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | Some USB3 devices are not showing up after suspend/resume cycles. In particular if a device uses a lower power state like U2 it may take longer to come up and the firmware needs to wait after sending a warm port reset. In addition skipping port reset to connected ports in the way into suspend was causing problems so instead send all ports a reset before suspend. BUG=chrome-os-partner:22402 BRANCH=falco,peppy,leon,wolf TEST=manual: Suspend/resume with ADATA HE720 HDD (and other devices) both connected at suspend and connecting while in suspend and ensure that the devices always show up in the kernel. Change-Id: Ib7b15dc65792742b4ceb7dcfc4b2c83192eafcc2 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/169548 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/6015 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* intel/lynxpoint: Export pch_enable_lpc() for Super I/O systemsStefan Reinauer2014-07-052-1/+2
| | | | | | | | | | | | | | | | | | | | | In order to enable a Super I/O in non Chrome EC systems we need to make pch_enable_lpc() available to the mainboard romstage.c BUG=none BRANCH=none TEST=boot ChromeOS on Beltino Change-Id: I34e7d23012e1852c69e82ba7cdc81a05751846de Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172180 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/6019 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
* intel/lynxpoint: Add SATA DEVSLP disable optionMarc Jones2014-07-042-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | Add the chip option to disable SATA DEVSLP. This disables the SDS bit in the SATA CAP2 register. BUG=chrome-os-partner:23186 BRANCH=leon TEST=Manual: System runs without SATA failure for more than 10 hours Original-Change-Id: I8baa40935421769aeee341a78441fb19ecaa3206 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: https://chromium-review.googlesource.com/174648 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> (cherry picked from commit 49d25812b04a983d687a53a39530559ba99fd9b4) Change-Id: Iac0b32f80958f5ffb571733484dc931bee216f55 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: https://chromium-review.googlesource.com/176352 Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/6013 Tested-by: build bot (Jenkins)
* intel/lynxpoint: Add CONFIG_LOCK_MANAGEMENT_ENGINE entry to KconfigDuncan Laurie2014-07-041-0/+13
| | | | | | | | | | | | | | | | This was missing from lynxpoint. BUG=chrome-os-partner:21796 BRANCH=falco,peppy TEST=emerge-falco chromeos-coreboot-falco Change-Id: Id1b261a5310ce1482f11c8c032c13f49046742fc Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66669 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/6012 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 21:55:10 +0000