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* treewide: Use 'fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk'Felix Held2022-10-157-7/+7
| | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaecb83c3bc9c75dab427a3ca54da1e6a8f87cf9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/68428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* treewide: Use 'fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk'Felix Held2022-10-1510-10/+10
| | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id3002dc976b82f71b1f60a6e32b16d60a7bbbead Reviewed-on: https://review.coreboot.org/c/coreboot/+/68427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* treewide: Use 'fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk'Elyes Haouas2022-10-1210-10/+10
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ic48c5c165732c8397c06a2362191a94ae5805cf1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* treewide: Use 'fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk'Elyes Haouas2022-10-1210-10/+10
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I7ddb4ea792b9a2153b7c77d2978d9e1c4544535d Reviewed-on: https://review.coreboot.org/c/coreboot/+/68275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* treewide: Use 'pm2_cnt_len' for 'x_pm2_cnt_blk.bit_width'Elyes Haouas2022-10-126-6/+6
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I040ddab8845cc2191c6ca5af7f132ec8a504bccf Reviewed-on: https://review.coreboot.org/c/coreboot/+/68274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* treewide: Use 'gpe0_blk' for 'x_gpe0_blk.addrl'Elyes Haouas2022-10-129-9/+9
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I05d5097097b925a7bc8058f4c23e7c13a49f03c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* treewide: Use 'gpe0_blk_len' for 'x_gpe0_blk.bit_width'Elyes Haouas2022-10-129-9/+9
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I581cacb6086d94fe65e6f4800454f447e1ada07b Reviewed-on: https://review.coreboot.org/c/coreboot/+/68272 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* treewide: Use 'fadt->pm_tmr_len' for 'x_pm_tmr_blk.bit_width'Elyes Haouas2022-10-129-9/+9
| | | | | | | | Change-Id: Id4e2939b74ec93f50a4bedd0069090f0775b0556 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68271 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* treewide: Use 'fadt->pm1_cnt_len' for 'x_pm1a_cnt_blk.bit_width'Elyes Haouas2022-10-129-12/+9
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I4e468e6bb58adc44bd66149eb79dc885dbf73c67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* treewide: Use 'fadt->pm1_evt_len' for 'x_pm1a_evt_blk.bit_width'Elyes Haouas2022-10-129-9/+9
| | | | | | | | Change-Id: I1e51ccad32f1c5e692c76b331eedf4d3bb260d38 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* treewide: use predicates to check for enabled pci devicesFabio Aiuto2022-10-066-6/+6
| | | | | | | | | | | | | use functions to check for pci devices instead of open-coded solution. TEST: compiled and qemu run successfully Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com> Change-Id: Idb992904112db611119b2d33c8b1dd912b2c8539 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68102 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/intel/common/gpio.c: Clean up includesElyes Haouas2022-10-061-3/+2
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Iba746431496b30daba098716337b688314eac283 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* sb/intel/i82801gx/bootblock.c: Clean up includesElyes Haouas2022-10-061-1/+2
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I61d4a188dc9526b71277c05dd317255fc9727414 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* sb/intel/i82801gx/early_init.c: Include common/rcba.hElyes Haouas2022-10-061-1/+3
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I5d9bc4ae942ba171a5d3ef4f77da69398fbac692 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* sb/intel/common/pmbase.c: Clean up includesElyes Haouas2022-10-061-4/+3
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ie23472d45c8232f5c907ec1757a648fa1a27d533 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68049 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* sb/intel/common/rtc.c: Clean up includesElyes Haouas2022-10-061-3/+4
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ibcd61e44f8e165627851e2c5325985f0765634b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* sb/intel/common/early_smbus.h: Add <device/pci_type.h>Elyes Haouas2022-10-061-0/+1
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Icf459f07948cd29eb251b49fcecefb98c5f5f259 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* treewide: use is_enabled_cpu() on cycles over device listFabio Aiuto2022-09-291-6/+1
| | | | | | | | | | | | | | | use is_enabled_cpu() on cycles over device list to check whether the current device is enabled cpu. TEST: compile test and qemu run successfully with coreinfo payload Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com> Change-Id: If64bd18f006b6f5fecef4f606c1df7d3a4d42883 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67797 Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* bd82x6x/early_pch: enable smbus in bootblock stageHusni Faiz2022-09-162-1/+8
| | | | | | | | | | | | SMBus is typically enabled in the ROMSTAGE. To get the BOOTBLOCK console message, the SMBus should be enabled in the BOOTBLOCK stage. Change-Id: I97d0afb013ede428383acaa0aa97ab04fe80e2a4 Signed-off-by: Husni Faiz <ahamedhusni73@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67340 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* timer: Change timer util functions to 64-bitRob Barnes2022-09-141-1/+1
| | | | | | | | | | | | | | | | | | | | Since mono_time is now 64-bit, the utility functions interfacing with mono_time should also be 64-bit so precision isn't lost. Fixed build errors related to printing the now int64_t result of stopwatch_duration_[m|u]secs in various places. BUG=b:237082996 BRANCH=All TEST=Boot dewatt Change-Id: I169588f5e14285557f2d03270f58f4c07c0154d5 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* amd/*/Makefile.inc: Put common words into common Makefile.incZheng Bao2022-09-011-5/+0
| | | | | | | | | | | | | Definition of FIRMWARE_LOCATION, POUND_SIGN, DEP_FILES, amd_microcode_bins are moved to common Makefile.inc. Change-Id: I5a0ea27002e09d0b879bafad37a5d418ddb4e644 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62658 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
* {sb,soc}/intel: Do not require hda_verb.cAngel Pons2022-08-236-12/+0
| | | | | | | | | | | Just use the conditional inclusion through `device/Makefile.inc`. Change-Id: Id363a97460ae2cfe4b10d491d4ef06394eb530c2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66609 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* southbridge: Add SPDX identifiers to files missing themMartin Roth2022-08-112-0/+6
| | | | | | | | | | | This adds SPDX identifiers to the remaining source files in the southbridge directory that don't already have them. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: If74aa82a7c40293198e07e81ceac52bd8ca8ad27 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66500 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/intel/bd82x6x/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer2022-07-292-5/+5
| | | | | | | | | | | Replace `LEqual(a, b)` with `a == b`. Change-Id: I4e219bea8df64db1d49beb8534f0f37fee0df5b6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
* sb/intel/i82801ix/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer2022-07-292-4/+4
| | | | | | | | | | | Replace `LEqual(a, b)` with `a == b`. Change-Id: Ifffd21a663739f72a5584e26b79b0627dd532d9e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
* sb/intel/i82801jx/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer2022-07-292-4/+4
| | | | | | | | | | | Replace `LEqual(a, b)` with `a == b`. Change-Id: I3aebd29bba285229979b79867c881018f61e2060 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
* sb/amd/cimx/sb800: Remove unused and unsafe macroAngel Pons2022-07-181-1/+0
| | | | | | | | | | | | | The `IMAGE_ALIGN` macro is unsafe because its value is compound and is not enclosed in parentheses, which can cause operation order problems. However, as this macro is unused, remove it instead of fixing it. Change-Id: I099c291f44d5a2c9d32c9ff071374016ed27eee8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* sb/amd/cimx: Fix some white spaces issuesElyes Haouas2022-07-188-41/+41
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Iba81be8ec48fa744f3263e340267a56158656a8f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* sb/amd/common: Fix some white spaces issuesElyes Haouas2022-07-172-5/+5
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I04951bf142fc4061960f42ad7ae702a70215e658 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* sb/amd/pi: Fix some white spaces issuesElyes Haouas2022-07-175-10/+10
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I90278683bc22d87364453f316c05afe4cd96b383 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* sb/amd/agesa: Fix some white spaces issuesElyes Haouas2022-07-174-6/+6
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I1497c7589570b8ff3873149a0fb212bad96ad432 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* sb/amd/*/*/smbus_spd.c: Fix some white spaces issuesElyes Haouas2022-07-173-50/+50
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I47ee16f2d4be34c42b2e7f9fa4c3a72a7a95967f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* sb/amd/*/*/sata.c: Fix some white spaces issuesElyes Haouas2022-07-172-6/+6
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I4c5dffb32e1ed858e93f95ed17eac894a9100501 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* sb/amd/*/*/smbus.h: Fix some white spaces issuesElyes Haouas2022-07-173-6/+6
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I18120ba93140e2dced7c8d9aafa34a834d1df842 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* sb/intel/ibexpeak: Perform const correctnessBill XIE2022-07-141-1/+1
| | | | | | | | | | me_bios_path_values[] in me.c should not be mutable. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I56412ff0883e1d37027b989c7ac1bd83e93661f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* commonlib: Substitude macro "__unused" in compiler.hBill XIE2022-07-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Since there are many identifiers whose name contain "__unused" in headers of musl libc, introducing a macro which expands "__unused" to the source of a util may have disastrous effect during its compiling under a musl-based platform. However, it is hard to detect musl at build time as musl is notorious for having explicitly been refusing to add a macro like "__MUSL__" to announce its own presence. Using __always_unused and __maybe_unused for everything may be a good idea. This is how it works in the Linux kernel, so that would at least make us match some other standard rather than doing our own thing (especially since the other compiler.h shorthand macros are also inspired by Linux). Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I547ae3371d7568f5aed732ceefe0130a339716a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
* soc,sb/amd: Change SPI controller resourceKyösti Mälkki2022-06-283-3/+3
| | | | | | | | | | This replaces IORESOURCE_SUBTRACTIVE with IORESOURCE_RESERVE. Change-Id: Ib3d934ca704273daacbeb3c52412bf04e2be7217 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64695 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device/resource: Add _kb postfix for resource allocatorsKyösti Mälkki2022-06-223-3/+3
| | | | | | | | | | | | There is a lot of going back-and-forth with the KiB arguments, start the work to migrate away from this. Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* intel/broadwell,lynxpoint: Change formula around 4 GiBKyösti Mälkki2022-06-221-1/+1
| | | | | | | | | | | Let's not rely on the type to get the correct result, casting 0 to 0ull made the result wrong. Change-Id: I6dfba3800170fdd4267e3bb74c55b05533c101fc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* sb/intel/i82801ix/smihandler.c: Remove dead incrementElyes Haouas2022-06-181-4/+0
| | | | | | | | | | | The value stored to 'data' is never read. So remove dead increment and commented out code. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ifef67fc6415af1260d1a1df54f53fbe67f8860bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/62541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* Replace some ENV_ROMSTAGE with ENV_RAMINITKyösti Mälkki2022-06-074-4/+4
| | | | | | | | | | | | | With a combined bootblock+romstage ENV_ROMSTAGE might no longer evaluate true. Change-Id: I733cf4e4ab177e35cd260318556ece1e73d082dc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63376 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* cpu/amd/agesa: Use common MRC_CACHE code to save S3 dataArthur Heymans2022-06-062-0/+2
| | | | | | | | | | | | | | | | Use the common code to save data for fast boot or S3 resume. An notable improvement that comes with this, is that the same 4K page is not rewritten all the time. This prolongs the hardware's life. TESTED on pcengines/apu1 and lenovo/g505s: S3 resume works fine. Change-Id: I0f4f36dcead52a6c550fb5e606772e0a99029872 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44295 Reviewed-by: Mike Banon <mikebdp2@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* sb/amd/agesa/hudson/hudson.c: Use BIT() macrosElyes Haouas2022-05-161-7/+8
| | | | | | | | | | Also, code reformatting to reduce coding style difference. Change-Id: I488050a6ab852520734b16032af9a683a3ad1a46 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* sb/amd/*/*/acpi: Reduce stylistic differencesElyes Haouas2022-05-165-16/+23
| | | | | | | | Change-Id: I1375b1d18113000b31266030fd7115e23d7cce5f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61875 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* soc/amd/*/Makefile.inc: Do some cosmeticsArthur Heymans2022-05-121-1/+1
| | | | | | | | | | | | The first target for the add_intermediate targets is always $(obj)/coreboot.pre. Change-Id: Iea2322ca1abd43900f3631b7965f07fed4235ca0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* vendorcode/amd/cimx/sb900: Drop codeArthur Heymans2022-05-111-1/+0
| | | | | | | | | | No mainboard is using this code. Change-Id: I4374360c211593a8468b6226f3d1729885b533e0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* arch/x86/acpi: Consolidate POST code handlingAngel Pons2022-05-041-7/+1
| | | | | | | | | | | | | Move ASL POST code declarations into a common file to avoid redundancy. Also, provide a dummy implementation when `POST_IO` is not enabled, as the value of `CONFIG_POST_IO_PORT` can't be used. Change-Id: I891bd8754f10f16d618e76e1ab88c26164776a50 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* sb/intel/i82801dx/pci.c: Use pci_or_config16() and macrosElyes Haouas2022-04-291-6/+1
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I658fa9cee4517b9f68102b74949d32d7ab0309f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* sb/intel/{i82371eb/i82801dx}: select BOOT_DEVICE_NOT_SPI_FLASHArthur Heymans2022-04-272-0/+2
| | | | | | | | | | | | SPI support started with Intel ICH7. Change-Id: I7cce5787e1241403e86c287273627b1c359ec94e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* southbridge/intel: Remove unused <acpi/acpi.h>Elyes HAOUAS2022-04-242-2/+0
| | | | | | | | | | | Found using: diff <(git grep -l '#include <acpi/acpi.h>' -- src/) <(git grep -l 'SLP_EN\|SLP_TYP_SHIFT\|SLP_TYP\|SLP_TYP_S\|ACPI_TABLE_CREATOR\|OEM_ID\|ACPI_DSDT_REV_\|acpi_device_sleep_states\|ACPI_DEVICE_SLEEP\|RSDP_SIG\|ASLC\|ACPI_NAME_BUFFER_SIZE\|COREBOOT_ACPI_ID\|acpi_tables\|acpi_rsdp\|acpi_gen_regaddr\|ACPI_ADDRESS_SPACE\|ACPI_FFIXEDHW_\|ACPI_ACCESS_SIZE_\|ACPI_REG_MSR\|ACPI_REG_UNSUPPORTED\|ACPI_HID_\|acpi_table_header\|MAX_ACPI_TABLES\|acpi_rsdt\|acpi_xsdt\|acpi_hpet\|acpi_mcfg\|acpi_tcpa\|acpi_tpm2\|acpi_mcfg_mmconfig\|acpi_hmat\|acpi_hmat_mpda\|acpi_hmat_sllbi\|acpi_hmat_msci\|acpi_srat\|ACPI_SRAT_STRUCTURE_\|acpi_srat_lapic\|acpi_srat_mem\|acpi_srat_gia\|CPI_SRAT_GIA_DEV_HANDLE_\|acpi_slit\|acpi_madt\|acpi_lpit\|acpi_lpi_flags\|acpi_lpi_desc_type\|ACPI_LPI_DESC_TYPE_\|acpi_lpi_desc_hdr\|ACPI_LPIT_CTR_FREQ_TSC\|acpi_lpi_desc_ncst\|acpi_vfct_image_hdr\|acpi_vfct\|acpi_ivrs_info\|acpi_ivrs_ivhd\|acpi_ivrs\|acpi_crat_header\|ivhd11_iommu_attr\|acpi_ivrs_ivhd_11\|dev_scope_type\|SCOPE_PCI_\|SCOPE_IOAPIC\|SCOPE_MSI_HPET\|SCOPE_ACPI_NAMESPACE_DEVICE\|dev_scope\|dmar_type\|DMAR_\|DRHD_INCLUDE_PCI_ALL\|ATC_REQUIRED\|DMA_CTRL_PLATFORM_OPT_IN_FLAG\|dmar_entry\|dmar_rmrr_entry\|dmar_atsr_entry\|dmar_rhsa_entry\|dmar_andd_entry\|dmar_satc_entry\|acpi_dmar\|acpi_apic_types\|LOCAL_APIC,\|IO_APIC\|IRQ_SOURCE_OVERRIDE\|NMI_TYPE\|LOCAL_APIC_NMI\|LAPIC_ADDRESS_\|IO_SAPIC\|LOCAL_SAPIC\|PLATFORM_IRQ_SOURCES\|LOCAL_X2APIC\|GICC\|GICD\|GIC_MSI_FRAME\|GICR\|GIC_ITS\|acpi_madt_lapic\|acpi_madt_lapic_nmi\|ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS\|acpi_madt_ioapic\|acpi_madt_irqoverride\|acpi_madt_lx2apic\|acpi_madt_lx2apic_nmi\|ACPI_DBG2_PORT_\|acpi_dbg2_header\|acpi_dbg2_device\|acpi_fadt\|ACPI_FADT_\|PM_UNSPECIFIED\|PM_DESKTOP\|PM_MOBILE\|PM_WORKSTATION\|PM_ENTERPRISE_SERVER\|PM_SOHO_SERVER\|PM_APPLIANCE_PC\|PM_PERFORMANCE_SERVER\|PM_TABLET\|acpi_facs\|ACPI_FACS_\|acpi_ecdt\|acpi_hest\|acpi_hest_esd\|acpi_hest_hen\|acpi_bert\|acpi_hest_generic_data\|acpi_hest_generic_data_v300\|HEST_GENERIC_ENTRY_V300\|ACPI_GENERROR_\|acpi_generic_error_status\|GENERIC_ERR_STS_\|acpi_cstate\|acpi_sw_pstate\|acpi_xpss_sw_pstate\|acpi_tstate\|acpi_lpi_state_flags\|ACPI_LPI_STATE_\|acpi_lpi_state\|acpi_upc_type\|UPC_TYPE_\|acpi_ipmi_interface_type\|IPMI_INTERFACE_\|ACPI_IPMI_\|acpi_spmi\|ACPI_EINJ_\|ACTION_COUNT\|BEGIN_INJECT_OP\|GET_TRIGGER_ACTION_TABLE\|SET_ERROR_TYPE\|GET_ERROR_TYPE\|END_INJECT_OP\|EXECUTE_INJECT_OP\|CHECK_BUSY_STATUS\|GET_CMD_STATUS\|SET_ERROR_TYPE_WITH_ADDRESS\|TRIGGER_ERROR\|READ_REGISTER\|READ_REGISTER_VALUE\|WRITE_REGISTER\|WRITE_REGISTER_VALUE\|NO_OP\|acpi_gen_regaddr1\|acpi_einj_action_table\|acpi_injection_header\|acpi_einj_trigger_table\|set_error_type\|EINJ_PARAM_NUM\|acpi_einj_smi\|EINJ_DEF_TRIGGER_PORT\|FLAG_PRESERVE\|FLAG_IGNORE\|EINJ_REG_MEMORY\|EINJ_REG_IO\|acpi_einj\|acpi_create_einj\|fw_cfg_acpi_tables\|preload_acpi_dsdt\|write_acpi_tables\|acpi_fill_madt\|acpi_fill_ivrs_ioapic\|acpi_create_ssdt_generator\|acpi_write_bert\|acpi_create_fadt\|acpi_fill_fadt\|arch_fill_fadt\|soc_fill_fadt\|mainboard_fill_fadt\|acpi_fill_gnvs\|acpi_fill_cnvs\|update_ssdt\|update_ssdtx\|acpi_fill_lpit\|acpi_checksum\|acpi_add_table\|acpi_create_madt_lapic\|acpi_create_madt_ioapic\|acpi_create_madt_irqoverride\|acpi_create_madt_lapic_nmi\|acpi_create_madt\|acpi_create_madt_lapics\|acpi_create_madt_lapic_nmis\|acpi_create_madt_lx2apic\|acpi_create_srat_lapic\|acpi_create_srat_mem\|acpi_create_srat_gia_pci\|acpi_create_mcfg_mmconfig\|acpi_create_srat_lapics\|acpi_create_srat\|acpi_create_slit\|acpi_create_hmat_mpda\|acpi_create_hmat\|acpi_create_vfct\|acpi_create_ipmi\|acpi_create_ivrs\|acpi_create_crat\|acpi_create_hpet\|acpi_write_hpet\|generate_cpu_entries\|acpi_create_mcfg\|acpi_create_facs\|acpi_create_dbg2\|acpi_write_dbg2_pci_uart\|acpi_create_dmar\|acpi_create_dmar_drhd\|acpi_create_dmar_rmrr\|acpi_create_dmar_atsr\|acpi_create_dmar_rhsa\|acpi_create_dmar_andd\|acpi_create_dmar_satc\|cpi_dmar_\|acpi_create_\|acpi_write_hest\|acpi_soc_get_bert_region\|acpi_resume\|mainboard_suspend_resume\|acpi_find_wakeup_vector\|ACPI_S\|acpi_sleep_from_pm1\|acpi_get_preferred_pm_profile\|acpi_get_sleep_type\|acpi_get_gpe\|permanent_smi_handler\|acpi_s3_resume_allowed\|acpi_is_wakeup_s3\|acpi_align_current\|get_acpi_table_revision' -- src/) |grep "<" Change-Id: I28de2bade9a0deb163364856b9f2eabe3d3a7a11 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-27 23:32:40 +0000