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* mb/*: Remove old USB configurations from SNB/bd82x6x boardsKeith Hui2024-06-081-1/+0
| | | | | | | | | | | | | Remove USB configurations and data structures from northbridge devicetree (SNB+MRC boards) and bootblock/romstage C code (native-only SNB boards). All USB configurations are drawn from southbridge devicetree going forward. Change-Id: Ie1cd21077136998a6e90050c95263f2efed68a67 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81882 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/sandybridge,sb/bd82x6x: Configure USB from southbridge devicetreeKeith Hui2024-06-083-2/+68
| | | | | | | | | | | | | | | | | | | | | | Transfer all USB responsibilities to southbridge/intel/bd82x6x, using one set of USB port configuration supplied by mainboards in the southbridge section of their devicetree. For MRC raminit, export southbridge_fill_pei_data() as a hook for southbridge code to implement. With new code via this hook, bd82x6x fills pei_data based on this one set of USB port config. For native raminit, early_usb_init() now goes directly to the devicetree and no longer get passed an address to it. TEST=abuild passes for all affected boards. All USB ports still work on asus/p8x7x-series/v/p8z77-m. Change-Id: I38378c7ee0701abc434b030dd97873f2af63e6b0 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81881 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/intel/bd82x6x/early_usb.c: Align native current map with MRCKeith Hui2024-06-072-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | | Replace 3 unused values in the map with those found during a Ghidra examination of MRC binary, and on hardwares running vendor firmware (asus/p8z77-m and HP Z210 CMT Workstation). The outgoing values were introduced in commit 216ad2170ca8 ("sb/intel/bd82x6x: Add new USB currents") in anticipation for Gigabyte GA-Z77-DS3H mainboard, but effort to land it was eventually abandoned. Since commit xxxxxxxxxxxx, such values can be placed directly in the port config, so there should be no hurdle should that effort be resurrected. Add a few #defines in pch.h to place some inline documentation on MRC values, but more will be documented in the future when this mapping is introduced MRC-side. Finally, update autoport to match. Change-Id: I195c7f627994e48f7a6e6698589504dc96248cff Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
* sb/intel/bd82x6x: Make space for USB port config in devicetreeKeith Hui2024-06-071-0/+2
| | | | | | | | | | | | | This is the first step to: - Move USB port configs, which are static, from C code to devicetree; - Unify USB port configs between MRC and native code path. Change-Id: I59af466d41790e2163342cac8676457ac19371ea Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81878 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/intel/bd82x6x: Allow actual USBIRx values for native USB configKeith Hui2024-06-071-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For USB to work under native code path, the USB port config needs to include a current setting for each port, which gets mapped to an initialization value that gets programmed into the USBIRx register for the respective port. This map resides in early_usb.c. The need to update it, whenever we see a previously unaccounted for initialization value, is getting out of hand. Instead this patch will allow specifying those values, presumably taken from an inteltool dump while running vendor firmware, directly in the USB port map. Because all USBIRx values are always in the 0x20000yyy form, we only need the lowest 12 bits. We have more than enough space in the USB port config structure for this. As the lowest yyy value we saw so far is 0x53, a note is included to limit the map to not more than 80 entries. Any value that is too big to be an index into the map is programmed directly, + 0x20000000, into the registers. This opens the future possibility to use the map for a simpler mapping for boards also using MRC, and remove the need for any mapping at all for the rest. Change-Id: I3d79b33bac742faa9bd4fc9852aff73fe326de4e Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
* tree: Use calloc(n, sizeof(struct)) insteadof calloc(sizeof(struct), n)Elyes Haouas2024-06-031-1/+1
| | | | | | | | Change-Id: I5e67e370d4eb8fe28227843bbca34db06ad84b26 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82786 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Revert "tree: Use Wcalloc-transposed-args command option"Elyes Haouas2024-06-031-1/+1
| | | | | | | | | | | | | This reverts commit b3db3abd6311924930f3250c9f9fc3157fbbf7da. Reason for revert: `Wcalloc-transposed-args` is new command option came with GCC-14. older versions will not support it. Change-Id: I74ef8de1f7d38e1e0519c3b41e79fd9b11d8e16f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82759 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree: Use <stdio.h> for snprintfElyes Haouas2024-05-292-0/+2
| | | | | | | | | | | | | <stdio.h> header is used for input/output operations (such as printf, scanf, fopen, etc.). Although some input/output functions can manipulate strings, they do not need to directly include <string.h> because they are declared independently. Change-Id: Ibe2a4ff6f68843a6d99cfdfe182cf2dd922802aa Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82665 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree: Use Wcalloc-transposed-args command optionElyes Haouas2024-05-291-1/+1
| | | | | | | | | | | | | GCC-14 documentation says "The first argument to calloc is documented to be number of elements in array, while the second argument is size of each element, so calloc(n, sizeof (int)) is preferred over calloc(sizeof(int), n)." Change-Id: I77b6f4d2eda487b087ba5665b588999633c33e8d Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82658 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/intel/bd82x6x/pch.asl: Remove GPIO configuration accessKeith Hui2024-04-181-25/+0
| | | | | | | | | | | | | Allowing access to change GPIO configuration from ACPI is asking for trouble. Kill it while nobody cares (yet). Access to mainpulate and blink GPIOs is maintained. Change-Id: Id80a7e2f815a58750623c133bb30e5ed84a6e2ed Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
* sb/intel/bd82x6x/pch.asl: Break out GPIO blink fieldKeith Hui2024-04-181-4/+32
| | | | | | | | | | | | Break out the individual bits of GPIO blink register as was done for GPIO level register. An upcoming patch will use this. Change-Id: I6f4749f60a9d569deba4b31f09f07a1321dabf4a Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81922 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
* sb/intel/ibexpeak: Drop USB3 settings from devicetreeKeith Hui2024-04-171-6/+0
| | | | | | | | | | | | | | | ibexpeak has no USB 3 capabilities. They were kept briefly when its devicetree structure was split from bd82x6x in commit ab4de83f4330 ("sb/intel/ibexpeak: Sever bd82x6x source dependency") to verify correctness. With that done, they can go. Change-Id: I6b847e1532d2e84a7b408a8858c8613b322d0373 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* sb/intel/ibexpeak: Sever bd82x6x source dependencyKeith Hui2024-04-162-5/+77
| | | | | | | | | | | | | | It shares southbridge devicetree definition with bd82x6x, causing changes made there to break builds for boards with this PCH. Give ibexpeak its own copy. TEST=abuild tested with lenovo/t410, lenovo/x201, packardbell/ms2290. Timeless binary did not change for all. Change-Id: I08229ca658bd9c360b6be6137d882d319041b730 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81889 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/intel/lynxpoint: Fix AER and L1 sub-state reportingAngel Pons2024-04-161-12/+14
| | | | | | | | | | | | | Program the AER capability header register in a single write because it's write-once. In addition, only PCH-LP supports L1 sub-states, so only report the L1 sub-state capability on PCH-LP. This follows what Lynx Point PCH reference code version 1.9.1 does. Change-Id: I08bd107eec7a3b2f1701c4657ae104e0818ae035 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57503 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/intel/lynxpoint/pcie.c: Fix 0xf5 register maskAngel Pons2024-04-161-1/+1
| | | | | | | | | | | Lynx Point PCH reference code version 1.9.1 masks the upper 4 bits of the PCIe root port register at offset 0xf5. Change-Id: I9529ad88d34a5cb4a09843e3165f3a70c5ea22e8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57502 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* lynxpoint/broadwell: Correct L1 exit latency with ASPMAngel Pons2024-04-161-4/+1
| | | | | | | | | | | | | Lynx Point PCH reference code version 1.9.1 programs the larger L1 exit latency when ASPM is enabled. Document 535127 (BDW PCH-LP BS) also does the same. Correct the condition accordingly. On Lynx Point, also remove a now-redundant write to the LCAP register (offset 0x4c). Change-Id: I2166bd5b5504ed97adcd2db0a802da02da4c91f3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57501 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/intel/bd82x6x: Add four new USB currentsJoel Linn2024-04-151-1/+2
| | | | | | | | | | | | | Found by inteltool on HP Pro 3500 Series running vendor firmware version 8.14 Rev.A. Change-Id: I156787e533c2605e7440548a2d3bf711bb1af5d7 Signed-off-by: Joel Linn <jl@conductive.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81427 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* lynxpoint/broadwell: Correct PCH-LP PCIe ASPM checkAngel Pons2024-04-141-5/+5
| | | | | | | | | | | | | Lynx Point PCH reference code version 1.9.1 checks bit 29 to detect ASPM on PCH-LP root port #6, not bit 28. Document 535127 (BDW PCH-LP BS) also uses bit 29 for root port #6. Correct the bit used in the check, as well as the surrounding comments. Change-Id: Ie4bd7cbbfc151762f29eab1326567f987b25ab19 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57500 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree: Drop duplicated <device/pci_{def,type}.h>Elyes Haouas2024-04-121-1/+0
| | | | | | | | | | <device/pci.h> is supposed to provide <device/pci_{def,type}.h> Change-Id: Ia645b8dba8c688187a25916f508593f333821f88 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81831 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* tree: Drop duplicated <device/{path,resource}.h>Elyes Haouas2024-04-127-7/+0
| | | | | | | | | | <device/device.h> is supposed to provide <device/{path,resource}.h> Change-Id: I2ef82c8fe30b1c1399a9f85c1734ce8ba16a1f88 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81830 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
* tree: Drop unused <halt.h>Elyes Haouas2024-04-113-3/+0
| | | | | | | | | | Change-Id: Icd00f30a96c53f70babdcb8a77c4b6c2868619d8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
* tree: Remove blank lines before '}' and after '{'Elyes Haouas2024-04-1111-12/+0
| | | | | | | | Change-Id: I46a362270f69d0a4a28e5bb9c954f34d632815ff Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* tree: Drop unused <elog.h>Elyes Haouas2024-04-101-1/+1
| | | | | | | | | | Change-Id: I40e2e5a786499abbe2fce63d6e0f1ac1e780ab51 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com>
* util/amdfwtool: build amdfwtool only for all tools or AMD CPUsMartin Roth2024-02-261-0/+1
| | | | | | | | | | | | When we're building non-AMD processors, don't bother building amdfwtool unless we're specifically building all of the tools like for abuild. Change-Id: I9021674a06d65a79e24020790d317ab947c505fe Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80714 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86/ioapic: use uintptr_t for IOAPIC base addressFelix Held2024-02-2310-21/+22
| | | | | | | | | | | | | | | Use uintptr_t for the IOAPIC base parameter of the various IOAPIC- related functions to avoid needing type casts in the callers. This also allows dropping the VIO_APIC_VADDR define and consistently use the IO_APIC_ADDR define instead. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I912943e923ff092708e90138caa5e1daf269a69f Reviewed-on: https://review.coreboot.org/c/coreboot/+/80358 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
* ec, lib, security, sb: Add SPDX license headers to Kconfig filesMartin Roth2024-02-184-0/+8
| | | | | | | | Change-Id: Ie63499a4b432803a78af1c52d49e34cf1653ba17 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80589 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/intel/i82371eb/isa: make IOAPIC ID constFelix Held2024-02-061-1/+1
| | | | | | | | | | | | Since the local IOAPIC ID variable is initialized as 2 and never changed afterwards, so make it const to make this more obvious. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1f19cc43b44a938758a43346f4fa75f8ed39ddea Reviewed-on: https://review.coreboot.org/c/coreboot/+/80349 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* lib: Move IP checksum to commonlibJulius Werner2024-02-021-1/+0
| | | | | | | | | | | | | | | | | | | | | | This patch moves the IP checksum algorithm into commonlib to prepare for it being shared with libpayload. The current implementation is ancient and pretty hard to read (and does some unnecessary questionable things like the type-punning stuff which leads to suboptimal code generation), so this reimplements it from scratch (that also helps with the licensing). This algorithm is prepared to take in a pre-calculated "wide" checksum in a machine-register-sized data type which is then narrowed down to 16 bits (see RFC 1071 for why that's valid). This isn't used yet (and the code will get optimized out), but will be used later in this patch series for architecture-specific optimization. Change-Id: Ic04c714c00439a17fc04a8a6e730cc2aa19b8e68 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80251 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
* device/device.h: Rename busses for clarityArthur Heymans2024-01-312-4/+4
| | | | | | | | | | This renames bus to upstream and link_list to downstream. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* include/device/device.h: Remove CHIP_NAME() macroNicholas Sudsgaard2024-01-3113-14/+14
| | | | | | | | | | | | | | | | | | | | | | | Macros can be confusing on their own; hiding commas make things worse. This can sometimes be downright misleading. A "good" example would be the code in soc/intel/xeon_sp/spr/chip.c: CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev, This appears as CHIP_NAME() being some struct when in fact these are defining 2 separate members of the same struct. It was decided to remove this macro altogether, as it does not do anything special and incurs a maintenance burden. Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* soc/intel: Unify the definition of TCO registersMarek Maslanka2024-01-302-9/+4
| | | | | | | | | | | | | | | | Move the definition of the TCO registers used in most boards to a separate file and use it consistently. Do not unify TCO for older incompatible platforms. BUG=b:314260167 TEST=none Change-Id: Id64a635d106cea879ab08aa7beca101de14b1ee6 Signed-off-by: Marek Maslanka <mmaslanka@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Jakub Czapiga <czapiga@google.com>
* device/device.h: Drop multiple linksArthur Heymans2024-01-291-7/+4
| | | | | | | | | | | | | | | | | | | | Multiple links are unused throughout the tree and make the code more confusing as an iteration over all busses is needed to get downstream devices. This also not done consistently e.g. the allocator does not care about multiple links on busses. A better way of dealing multiple links below a device is to feature dummy devices with each their respective bus. This drops the sconfig capability to declare the same device multiple times which was previously used to declare multiple links. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Iab6fe269faef46ae77ed1ea425440cf5c7dbd49b Reviewed-on: https://review.coreboot.org/c/coreboot/+/78328 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jincheng Li <jincheng.li@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* southbridge: Rename Makefiles from .inc to .mkMartin Roth2024-01-2419-0/+0
| | | | | | | | | | | | | | | | | The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic80d27a963da8eddc3d1f0d9a3d59763028d4ed0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/80075 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* sb/intel/bd82x6x: Rework PCH ID cacheAngel Pons2024-01-181-4/+4
| | | | | | | | | | | | | | Work around a romstage restriction. Globals (or static variables) cannot be initialized to a non-zero value because there's no data section. Note that the revision ID for stepping A0 is zero, so `pch_silicon_revision` will no longer use the cached value for this PCH stepping. Since it is a pre-production stepping, it is most likely not used anywhere anymore. Change-Id: I07663d151cbc2d2ed7e4813bf870de52848753fd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* sb/intel/i82801{i,j}x/chip.h: Use boolean where appropriateElyes Haouas2024-01-154-13/+13
| | | | | | | | | | Change-Id: I867451ae3d6d37033c9e0e57a4d7fd4a06dedbef Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77738 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
* sb/intel/bd82x6x/sata: Enable SATA clock gatingPatrick Rudolph2024-01-151-0/+4
| | | | | | | | | | | | | | | Program SATA IOBP and enable clock gating after port enable bits have been written. The same registers are already set for DMI and PCIe. TEST: Lenovo X220 still boots over SATA. Change-Id: I50970117ddcf8d39796426a19c1a6b57e5b1e690 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79146 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/intel/bd82x6x/early_usb: Add USB TX/RX gainsPatrick Rudolph2024-01-152-6/+19
| | | | | | | | | | | | | | | Describe the USB 'current' settings based on MRC.bin that converts the USB trace length to a predefined register value. MRC.bin decides which setting to use based on the PC type, mobile or desktop, and the trace length. Tested: Lenovo X220 still boots. Change-Id: I79d35ca16818daec03ee7f464349a4c8ee0f78e4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* sb/intel/bd82x6x/early_usb: Print error for invalid USB settingPatrick Rudolph2024-01-151-2/+17
| | | | | | | | | | | | | | | | According to BWG the USB current setting 0 should not be used for desktop boards. As autoport defaults to 0 if the USB current doesn't match one of the lookup table entries most of the desktop boards in tree have such a setting. Print an error to alert users of such boards to update the USB current settings. Tested: Lenovo X220 still boots. Change-Id: If76e9126b4aba8e16c1c91dece725aac12e1a7e9 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78827 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/intel: Use boolean for pcie_hotplug_map attributeFelix Singer2024-01-145-5/+10
| | | | | | | | Change-Id: Ia5e1ee683fa3d8d216ece26426e9870981ede2ba Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79932 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/intel/bd82x6x: Remove dummy SOUTH_BRIDGE_OPTIONS Kconfig symbolElyes Haouas2024-01-121-10/+12
| | | | | | | | | Change-Id: If4ae9c800325f5de8f170f8922bacffad1c9bb20 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77532 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* sb/amd/pi/hudson/Kconfig: replace HUDSON_LEGACY_FREE optionFelix Held2024-01-122-11/+16
| | | | | | | | | | | | | | | | HUDSON_LEGACY_FREE controlled both if the legacy devices and the 8042 flags are set in the IA-PC boot architecture filed of the FADT. Since some systems have legacy devices on the LPC bus, but no 8042-compatible keyboard controller, replace this option with the two new options HUDSON_FADT_LEGACY_DEVICES and HUDSON_FADT_8042. TEST=The FACP table doesn't change on APU2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id4ff85630c90fb2ae8c8826bbc9049a08668210d Reviewed-on: https://review.coreboot.org/c/coreboot/+/79893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* sb/amd/pi/hudson/smhandler: use apm_get_apmc() in APMC SMI handlerFelix Held2024-01-101-1/+1
| | | | | | | | | | | | Instead of open-coding this functionality and using non-common defines, call the apm_get_apmc() helper function. This also brings this more in line with the newer AMD SoCs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic16596404f46bf431e1c5db56859ddfea5fccbf8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79850 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* sb/amd/pi/hudson: select HAVE_CONFIGURABLE_APMC_SMI_PORTFelix Held2024-01-102-0/+8
| | | | | | | | | | | | | | Select HAVE_CONFIGURABLE_APMC_SMI_PORT and implement the pm_acpi_smi_cmd_port helper function. TEST=APU2 still compiles with HAVE_SMI_HANDLER selected and NO_SMM select removed. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8f79d8c1d59aa1b6c1145dd0b1cbc9010a1c57e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* sb/amd/pi/hudson/smhandler: use common APM_CNT_ACPI_* definesFelix Held2024-01-102-4/+2
| | | | | | | | | | | | | | | | The Hudson southbridge code for the AMD binaryPI SoCs had its own ACPI enable and disable APMC command numbers that didn't match the common defines in coreboot, so use the common define here to be consistent with the command numbers in the corresponding FADT fields. Since the only SoC that still would use this code doesn't select HAVE_SMI_HANDLER, this won't fix any observable bug, but better fix this before anyone possibly runs into this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5e596071e1b5269b616b7a93151648cb86ae77bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/79848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* sb/amd/pi/hudson: drop unused ACPI_SMI_CMD_* definesFelix Held2024-01-101-3/+0
| | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Idf02d8bee70fd654b3e71d1ead6dc0414fb6de40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79847 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/amd/pi/hudson: fix gpio.h and smi.h include locationFelix Held2024-01-103-0/+2
| | | | | | | | | | | | | | | | This fixes the following compile error when trying to build the APU2 board with HAVE_SMI_HANDLER selected and the NO_SMM select removed: In file included from src/soc/amd/common/block/gpio/gpio.c:8: src/include/gpio.h:6:10: fatal error: soc/gpio.h: No such file or directory 6 | #include <soc/gpio.h> /* IWYU pragma: export */ | ^~~~~~~~~~~~ Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie06044b12f5cbcc55a2706ec566afd2eb294c62b Reviewed-on: https://review.coreboot.org/c/coreboot/+/79846 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/intel/bd82x6x/pch: Add method to identify PCHPatrick Rudolph2023-12-262-0/+22
| | | | | | | | | | | | | Identify PCH type by LPC device ID. This allows to identify the PCH without including northbridge headers. Tested: Lenovo X220 still boots. Change-Id: Ic3e15c1d8d4b1d1012d6204cc65de92d91431fbe Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* sb/intel/bd82x6x: Add defines for PCI IDsPatrick Rudolph2023-12-231-37/+38
| | | | | | | | | | Add and use defines for 6 series and 7 series PCH PCH IDs. Change-Id: I4de37d5817766b9bc4f5c2d4d472d3c456b14b29 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79546 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/intel/bd82x6x: Honor POST code Kconfig optionKeith Hui2023-12-231-4/+7
| | | | | | | | | | | | | | | | | This southbridge can route POST codes written to port 0x80 to either LPC or PCI, but currently always route them to LPC. Change it so that POST codes are routed to PCI if CONFIG(POST_DEVICE_PCI_PCIE) is selected, LPC otherwise. Rename the static function because POST codes no longer always go to LPC. Change-Id: I455d7aff27154d6821e262a21248e8c7306e2d61 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nico Huber <nico.h@gmx.de>
* nb,sb/amd/pi/*/pci_devs: drop unused PCI device IDsFelix Held2023-12-201-9/+0
| | | | | | | | | | | | | SATA_IDE_DEVID, AHCI_DEVID_MS and AHCI_DEVID_AMD are still kept even though they're unused at the moment, but those might still be useful to keep around, since the SATA controller can have different PCI device IDs depending on in which mode it is in. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia05683b732d9748d9198225acaecbd4dc196733a Reviewed-on: https://review.coreboot.org/c/coreboot/+/79577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-02 10:11:35 +0000