| Commit message (Collapse) | Author | Age | Files | Lines |
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Move the verstage on PSP files in vendorcode from the fsp subdirectory
to a new psp_verstage subdirectory, since those files aren't specific to
the case of the FSP being used for the silicon initialization.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic47f8b18bc515600add7838f4c7afcb4fff7c004
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80209
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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To assist in debugging, add a way for PSP_verstage to send postcodes to
the system.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I22e45e26f599a0b4f0b781e9b97fccb68e2e5cc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Add an SVC call to get the state of Hardware Security Processor (HSP) in
AMD SoCs. This SVC call will be used from PSP verstage to get and
report HSP state.
BUG=b:198711349
TEST=Build Skyrim BIOS image and boot to OS. Ensure that the HSP state
is read and reported in the firmware logs.
Change-Id: I7fe3363d308a80cc09e6bdadd8d0bb1d67f7d2bf
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71207
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add an SVC command to get the previous boot status. If there is any
pre-x86 boot failure in the previous boot cycle, PSP stores it in warm
reset persistent register and triggers a warm reset. PSP verstage on the
subsequent boot gets the previous boot status and reports any failure to
the vboot before a FW slot is selected.
BUG=b:242825052
TEST=Build Skyrim BIOS image and boot to OS in Skyrim. Trigger a failure
scenario by corrupting certain firmware blobs and observe that PSP
reports the failure boot status. On a normal boot, observed that PSP
reports successful boot.
Change-Id: I440deee560b72c80491bfdd7fda38a1c3a4299e5
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70381
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new PSP svc call to pass psp firmware hash table to the PSP.
psp_verstage will verify hash table and then pass them to the PSP.
The PSP will check if signed firmware contents match these hashes.
This will prevent anyone replacing signed firmware in the RW region.
BUG=b:203597980
TEST=Build and boot to OS in Skyrim.
Change-Id: I512d359967eae925098973e90250111d6f59dd39
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67259
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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'Mendocino' was an embargoed name and could previously not be used
in references to Skyrim. coreboot has references to sabrina both
in directory structure and in files. This will make life difficult
for people looking for Mendocino support in the long term. The code
name should be replaced with "mendocino".
BUG=b:239072117
TEST=Builds
Cq-Depend: chromium:3764023
Cq-Depend: chromium:3763392
Cq-Depend: chrome-internal:4876777
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I2d0f76fde07a209a79f7e1596cc8064e53f06ada
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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