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* vc/mediatek/mt8195: Remove unused codeRyan Chuang2021-09-032-2029/+1
* wifi: Add support for DSM methods for intel wifi cardSugnan Prabhu S2021-09-021-0/+10
* wifi: Add support for wifi time average SAR configSugnan Prabhu S2021-09-021-0/+15
* wifi: Add support for per-platform antenna gainSugnan Prabhu S2021-09-021-0/+27
* wifi: Add support for new revisions of SAR table entriesSugnan Prabhu S2021-09-021-41/+203
* AGESA f15tn: Fix building IDS tracing supportAngel Pons2021-08-2216-38/+37
* AGESA f15tn: Hook up IDS options to KconfigAngel Pons2021-08-222-26/+61
* AGESA f15tn: Factor out common OptionsIds.hAngel Pons2021-08-222-1/+33
* AGESA f15tn: Drop `IDSOPT_ASSERT_ENABLED`Angel Pons2021-08-223-80/+0
* vc/mediatek/mt8195: Optimize DRAM init time by disabling Vcore settingRyan Chuang2021-08-121-3/+4
* vc/mediatek/mt8195: Optimize DRAM init time by reducing I2C I/ORyan Chuang2021-08-091-0/+2
* vc/mediatek/mt8195: Optimize DRAM init time by limiting frequency countRyan Chuang2021-08-091-0/+3
* vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2265_01Ronak Kanabar2021-07-302-30/+32
* vc/intel/fsp/fsp2_0/alderlake: Update MemInfoHob.h for new FSPEric Lai2021-07-291-14/+17
* src/vendorcode/eltan: Don't reference CONFIG_CBFS_SIZEArthur Heymans2021-07-281-1/+8
* vc/mediatek/mt8195: Improve DRAM stability by impedance trackingRyan Chuang2021-07-281-1/+5
* soc/amd/cezanne: enable crypto in psp_verstageKangheui Won2021-07-211-0/+52
* vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2237_00Ronak Kanabar2021-07-132-15/+22
* vc/mediatek/mt8195: Remove redundant codeRyan Chuang2021-07-131-10/+1
* vc/amd/sb800: Cast to UINT32 for shift out of bounds fixPaul Menzel2021-07-121-3/+3
* vc/amd/sb800: Cast variable to 32-bit before shiftPaul Menzel2021-07-121-44/+44
* vc/amd/sb800: SBCMN: Cast to 32-bit before shiftPaul Menzel2021-07-121-6/+6
* vc/mediatek/mt8195: Enable DRAM Vcore DVFS settingsRyan Chuang2021-07-122-2/+6
* vc/mediatek/mt8195: add FOR_COREBOOT defineRex-BC Chen2021-07-122-10/+13
* vc/mediatek/mt8195: Enable VREF calibration at DDR3200 for S0 stabilityRyan Chuang2021-07-071-1/+1
* vc/mediatek/mt8195: Improve settings of duty calibrationRyan Chuang2021-07-072-10/+18
* timestamp,vc/google/chromeos/cr50: Add timestamp for enable updateRaul E Rangel2021-07-051-1/+6
* vc/mediatek/mt8195: Fix license headersRex-BC Chen2021-06-3041-984/+66
* vendorcode/intel/fsp: Remove deprecated headerRonak Kanabar2021-06-261-68/+0
* edk2-stable202005: Update MdePkg/Include/IndustryStandard/SmBios.hRonak Kanabar2021-06-251-0/+3
* vc/mediatek/mt8195: Allow adjusting DRAM voltage in DRAM calibrationRyan Chuang2021-06-241-17/+26
* vc/amd/fsp/cezanne/FspmUpd: add hda_enable UPDFelix Held2021-06-211-1/+2
* vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2207_01Ronak Kanabar2021-06-212-108/+121
* vc/mediatek/mt8195: Match definition with declarationPatrick Georgi2021-06-151-1/+1
* vc/mediatek/mt8195: Fix code indentationPatrick Georgi2021-06-151-2/+2
* ACPI: Refactor use of global and device NVSKyösti Mälkki2021-06-141-2/+0
* ChromeOS: Separate NVS from global GNVSKyösti Mälkki2021-06-142-14/+19
* soc/amd/cezanne: Supply SMBIOS/DMI Type 17 dataNikolai Vyssotski2021-06-131-0/+236
* vc/intel/fsp/fsp2_0/alderlake: Update MemInfoHob.h for new FSPEric Lai2021-06-101-0/+26
* vc/intel/fsp2_0/tigerlake: Remove unused headersFelix Singer2021-06-105-8168/+0
* soc/amd/common/fsp/pci: Add size field to PCIe interrupt routing HOBNikolai Vyssotski2021-06-071-2/+2
* cezanne/psp_verstage: add reset/timer svcKangheui Won2021-06-071-0/+35
* vendorcode/intel/fsp: Update to include post PRQ UPDs for Tiger LakeSrinidhi N Kaushik2021-05-282-201/+2138
* vc/amd/pi/00630F01: Remove unused directory and codeMichał Żygowski2021-05-2636-17356/+2
* soc/amd/cezanne: add support for the changed AMD FSP API for USB PHYJulian Schroeder2021-05-262-21/+63
* vendorcode/intel/fsp: Add Elkhart Lake FSP headers for FSP v3162Tan, Lean Sheng2021-05-264-865/+933
* soc/amd/cezanne,common,picasso: use BERT region reserved by FSP driverFelix Held2021-05-212-8/+0
* vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2162_00Ronak Kanabar2021-05-162-1082/+1084
* vendor/mediatek: Add MT8195 dram initialization codeRyan Chuang2021-05-1446-0/+96771
* vc/mediatek: Align code indent with code flowPatrick Georgi2021-05-131-2/+2
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