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* vendorcode/mediatek/mt8195: Fix set but unused variablesArthur Heymans2023-05-131-1/+1
| | | | | | | | Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I5738e73f2121e2558831fbaa9c92a2fd0926ad88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* vendorcode/mediatek/mt8195: More sure ucDoneFlg is initializedArthur Heymans2023-05-131-1/+1
| | | | | | | | | | | One some codepaths ucDoneFlg is not initialized. This fixes a clang warning. Change-Id: I78aa2c711626b24f003f5c95b1c9598eaff7cb1b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* vendorcode/mediatek/mt8195: Make order of operators more explicitArthur Heymans2023-05-131-1/+1
| | | | | | | | | | Clang warns about this. Change-Id: I9a19f33df64a63e51e3dadac4aae28a8bb12121d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* vendorcode/mediatek/mt8195: Fix superfluous bracketsArthur Heymans2023-05-132-2/+2
| | | | | | | | | | Clang warns about this. Change-Id: I4310737bd63728d3c592d0f4d1030bc352afa575 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* vendorcode/mediatek/mt8195: Fix casting enum of different typesArthur Heymans2023-05-131-3/+2
| | | | | | | | | | Clang warns about this. Change-Id: I18ff23c3c18b7cd74f0d6fe0b308b9096ce269ae Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* vendorcode/mediatek/mt8195: Fix set but unused variablesArthur Heymans2023-05-138-46/+24
| | | | | | | | | | The clang compiler warns about this. Change-Id: I1584258aa24d6a0bf558b3c622bc53c156a37b09 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* vendorcode/cavium: Fix additions to stringArthur Heymans2023-05-131-1/+1
| | | | | | | | | | | | | | The clang compiler is confused about adding integers to strings. Adding brackets around the macros fixes this. TEST: BUILD_TIMELESS=1 remains the same. Change-Id: I2ea17322352d977bf0ec3ee71b14463fa218d07c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74541 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vendorcode/mediatek/mt8192: Fix set but unused variablesArthur Heymans2023-05-136-23/+6
| | | | | | | | | | TEST: BUILD_TIMELESS=1 binary remains the same. Change-Id: Ic05a9819764c03184b54c4fc58dbe325fddeae10 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* vendorcode/mediatek/mt8192: Fix set but unused variablesArthur Heymans2023-05-131-36/+11
| | | | | | | | | | | The binary does change on these with BUILD_TIMELESS. Change-Id: I45d51d53f991556cedd1cc45997d76fc828bceb5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74544 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* vendorcode/cavium: Fix set but unused variablesArthur Heymans2023-05-123-18/+2
| | | | | | | | | | | | TEST: BUILD_TIMELESS=1 remains the same. Change-Id: Id2cb37dbe4d450fe7f91a527b5cd73ac55863548 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74542 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* vc/intel/fsp/mtl: Update header files from 3084_85 to 3165_81Kilari Raasi2023-05-112-787/+784
| | | | | | | | | | | | | | | | | | | | | | | | | | Update header files for FSP for Meteor Lake platform to version 3165_81, previous version being 3084_85. FSPM: 1. Change UPD name from 'GtExtraTurboVoltage' to 'GtAdaptiveVoltage' 2. Change UPD name from 'CoreVoltageAdaptive' to 'CoreAdaptiveVoltage' 3. Change UPD name from 'RingVoltageAdaptive' to 'RingAdaptiveVoltage' 4. Address offset changes FSPS: 1. Remove deprecated UPD 'PcieDpc' 2. Address offset changes BUG=b:280005256 TEST=Able to build and boot google/rex to ChromeOS. Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Change-Id: I67939ecf71166fca4f3d2d6cd4622215bebc5718 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* vc/google: Decouple DSM_CALIB from CHROMEOSMatt DeVillier2023-05-057-29/+41
| | | | | | | | | | | | | | | | | | | | | | | DSM (Dynamic Speaker Management) uses calibration parameters stored in a VPD (Vital Product Data) FMAP region to configure the audio output via an ACPI _DSD table. This has no dependency on a ChromeOS, and can be used by Linux/Windows drivers if appropriately configured. Remove the dependency of DSM_CALIB (and the calibration file) on CHROMEOS and replace it with VPD, so that non-CHROMEOS builds can utilize this feature as well. Move files from underneath vc/google/chromeos to underscore the point. TEST=build/boot google/nightfury, dump ACPI, verify DSM calibraton parameters present in _DSD table. Change-Id: I643b3581bcc662befc9e30736dae806f94b055af Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74812 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* vendorcode/mediatek/mt8192: Cast enum typesArthur Heymans2023-05-011-6/+6
| | | | | | | | | | | | Clang warns about using the wrong enum types as arguments. Change-Id: Idfebf2f6deec7d531cbda6667384b5f591bdc3cb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74546 Reviewed-by: Xixi Chen <xixi.chen@mediatek.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com>
* vc/amd/fsp/mendocino/FspmUpd: Add UPD to set eDP panel T9 vauleChris Wang2023-04-271-1/+2
| | | | | | | | | | | | | | | | | Add UPD edp_panel_t9_ms for eDP panel sequence adjustment. BUG=b:271704149 BRANCH=Skyrim Test=Build/Boot to ChromeOS Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Idc1a212e9c203584a6497fd6cbd3f995eeb030f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74788 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/mendocino: rename pwr_on_vary_bl_to_blon to edp_panel_t8_msChris Wang2023-04-271-2/+2
| | | | | | | | | | | | | | | | | | Rename the UPD pwr_on_vary_bl_to_blon to edp_panel_t8_ms to match the eDP sequence timing in milliseconds. BUG=b:271704149 BRANCH=Skyrim Test=Build/Boot to ChromeOS Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Iecdfe47cd9142d8a1ddeee0ec988d37b2a11028e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74787 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* vendorcode/mediatek/mt8192: Add or remove bracketsArthur Heymans2023-04-242-2/+2
| | | | | | | | | | | | | | This fixes clang compilation warnings about logic problems and superfluous brackets. Change-Id: Ib4333b834ee2afb3147edf4c223724a851f159ba Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Xixi Chen <xixi.chen@mediatek.corp-partner.google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* vc/google/chromeec/acpi: write OIPG in DECLARE_NO_CROS_GPIOS caseFelix Held2023-04-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a mainboard selects ACPI_SOC_NVS and CHROMEOS, CHROMEOS_NVS will be selected. This causes vc/google/chromeec/acpi/chromeos.asl to be included in the DSDT and chromeos_acpi_gpio_generate to be called when generating the coreboot SSDT. When a mainboard also uses DECLARE_NO_CROS_GPIOS(), this will cause variant_cros_gpio.count to be 0 and variant_cros_gpio.gpios to be NULL. chromeos_acpi_gpio_generate only checked if the GPIO table was non-NULL, which caused the function to exit early and not generate the OIPG package which causes the kernel to complain about referencing the non-existing OIPG package. To avoid this, only exit in the GPIO table pointer being NULL case if the number of GPIOs is non-0. TEST=Error about missing OIPG ACPI object in dmesg disappears on birman. Before: [ 0.241339] chromeos_acpi: registering CHSW 0 [ 0.241468] ACPI BIOS Error (bug): Could not resolve symbol [\CRHW.GPIO.OIPG], AE_NOT_FOUND (20220331/psargs-330) [ 0.241703] ACPI Error: Aborting method \CRHW.GPIO due to previous error (AE_NOT_FOUND) (20220331/psparse-531) [ 0.241933] chromeos_acpi: failed to retrieve GPIO (5) [ 0.242011] chromeos_acpi: registering VBNV 0 [ 0.242113] chromeos_acpi: registering VBNV 1 [ 0.242284] chromeos_acpi: truncating buffer from 3072 to 1336 [ 0.242462] chromeos_acpi: installed With the patch applied: [ 0.242580] chromeos_acpi: registering CHSW 0 [ 0.242714] chromeos_acpi: registering VBNV 0 [ 0.242817] chromeos_acpi: registering VBNV 1 [ 0.242990] chromeos_acpi: truncating buffer from 3072 to 1336 [ 0.243249] chromeos_acpi: installed Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ie340003afb718b1454c2da4a479882b71714c3c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74375 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vc/amd/fsp/mendocino/FspmUpd: Update UDP structure for MDN-FSPChris.Wang2023-03-291-1/+2
| | | | | | | | | | | | | | Update UPD structure to align with MDN-FSP. BUG=b:271704149 BRANCH=none TEST=Build/Boot to Chrome OS Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ie4021cebb57e3ec22191486aafd9099eec0fbd99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73751 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
* vc/intel/fsp/mtl: Update header files from 3064_81 to 3084_85Kilari Raasi2023-03-293-251/+257
| | | | | | | | | | | | | | | | | | | | | | | | | | | Update header files for FSP for Meteor Lake platform to version 3084_85, previous version being 3064_81. FirmwareVersionInfo.h: 1. Define INTEL_FVI_SMBIOS_TYPE macro FSPM: 1. Remove deprecated UPD `BclkSource` 2. Address offset changes FSPS: 1. Add `CnviWifiCore` UPD 2. Address offset changes BUG=b:274051289 TEST=Able to build and boot google/rex to ChromeOS. Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Change-Id: I24dea1a31dbb592f9dea4246a3d490e5d23dca9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/73832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* vc/amd/fsp/mendocino:Add fch_usb_3_port_force_gen1 tp AGESA FSP-M UPDPatrick Huang2023-03-271-1/+2
| | | | | | | | | | | | | | To add fch_usb_3_port_force_gen1 parameter to force usb3 port to gen1 BUG=b:273841155 BRANCH=None TEST=Build Change-Id: I7560abb9a5fda6af3c2814f8b26c92925d8c17f4 Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/mendocino: Add UPDs for DPTC current limitsPatrick Huang2023-03-271-1/+4
| | | | | | | | | | | | | | | | Add UPD vrm_current_limit_mA, vrm_maximum_current_limit_mA, vrm_soc_current_limit_mA for DPTC. Make sure UPD parameterare are set to be aligned. BUG=b:245942343 BRANCH=none TEST=confirm the UPD parameters has been set correspondingly with the FSP UPD. Change-Id: Iacf0ce0d51d4c8698ec1ae7e810fd00574deeadb Signed-off-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73875 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/intel/xeon_sp/uncore_acpi.c: Add SPR-SP supportTim Chu2023-03-252-0/+7
| | | | | | | | | | | | | | Add support for Intel SPR-SP to uncore_acpi.c. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Signed-off-by: Shelly Chang <Shelly_Chang@wiwynn.com> Change-Id: I4c436a60743bee21b3b6e4060d7874a6cdc75ecf Reviewed-on: https://review.coreboot.org/c/coreboot/+/71958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* soc/amd/mendocino: Consume fsp misc_data hobJason Glenesk2023-03-201-0/+4
| | | | | | | | | | | | | | | Provide support function to query fsp misc_data hob and return smu reported power and thermal limit. BUG=b:253301653 TEST=Use get_amd_smu_reported_tdp(&tdp) values match what FSP placed in the hob. Change-Id: I9f0d8cdd616726c5a714e99504b83b0126dd273b Signed-off-by: Jason Glenesk <jason.glenesk@amd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73747 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vc/intel/fsp/mtl: Add tCCD_L_WR to MemInfoHob as per FSP v3064Subrata Banik2023-03-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | This patch updates the Memory Hob Info data structure as per FSP v3064 source code change. BUG=b:273894357 TEST=Able to see `smbios type 17` table while booting google/rex. Without this patch: [DEBUG] 0 DIMM found With this patch: [DEBUG] 8 DIMM found Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3885fa7143cecc0b56e20278b69951c548ac451b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73755 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* vc/intel/fsp/mtl: Update header files from 2523_80 to 3064_81Kilari Raasi2023-03-083-978/+1012
| | | | | | | | | | | | | | | | | | | | | | | | | | | Update header files for FSP for Meteor Lake platform to version 3064_81, previous version being 2523_80.. FSPM: 1. Addition of new UPDs SocTraceHubMode,SocTraceHubMemReg0Size SocTraceHubMemReg1Size. 2. Remove depricated UPD RDODTT. 3. Address offset changes. FSPS: 1. Address offset changes. FspUpd.h: 1.Corrected UPD signatures. BUG=b:TBD Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Change-Id: I73764d471295ad1a969ae562fe8a9fb7a25c5b2a Reviewed-on: https://review.coreboot.org/c/coreboot/+/73374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
* vc/siemens/hwilib: Change uint32_t return type to size_tJan Samek2023-03-022-5/+5
| | | | | | | | | | | | | | | | | | | | | | The commit fcff39f0ea47 ("vc/siemens/hwilib: Rename 'maxlen' to 'dstsize'") changed the 'dstsize' input parameter type from uint32_t to size_t. This patch changes also the return parameter, which is often directly compared with the aforementioned input parameter value. This should introduce no change on 32-bit builds and stay consistent across the project in the case of 64-bit builds and avoid comparisons of integers of different width here. BUG=none TEST=No changes to hwilib behavior on any of the siemens/mc_apl1 or siemens/mc_ehl variants. Change-Id: I0a623f55b596297cdb6e17232828b9536c9a43e6 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
* vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP RPL.4031.01Bora Guvendik2023-02-231-180/+190
| | | | | | | | | | | | | | | | The headers added are generated as per FSP v4031.01 BUG=b:270416522 BRANCH=firmware-brya-14505.B TEST=Boot to OS Cq-Depend: chrome-internal:5513169, chrome-internal:5511170 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ia21807ee71c98489fd96f870c2d61f54e094c3d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
* vc/intel/fsp/mtl: Update header files from 2473_86 to 2523_80Kilari Raasi2023-02-172-788/+809
| | | | | | | | | | | | | | | | | | | | | | | Update header files for FSP for Meteor Lake platform to version 2523_80, previous version being 2473_86. FSPM: 1. Rename DMI UPDs 2. Address offset changes FSPS: 1. Address offset changes BUG=b:266499304 Change-Id: Ib4b8478bc3558ef863b6b52e685f981a5891e4a9 Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72591 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* soc/amd/mendocino: Add svc_write_postcode call instead of stubMartin Roth2023-02-131-0/+1
| | | | | | | | | | | To assist in debugging, add a way for PSP_verstage to send postcodes to the system. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I22e45e26f599a0b4f0b781e9b97fccb68e2e5cc1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* tree: Drop repeated wordsAlexander Goncharov2023-02-071-1/+1
| | | | | | | | | | | | | Found-by: linter Change-Id: I7c6d0887a45fdb4b6de294770a7fdd5545a9479b Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72795 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vc/amd/pi: Fix "No such file or directory"Elyes Haouas2023-02-052-24/+27
| | | | | | | | | | | | | | | | | | | | Fix: cc1: error: src/vendorcode/amd/pi/00670F00: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/binaryPI: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/Include: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/Proc: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/Proc/Common: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/Proc/CPU: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/Proc/CPU/Family: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/Proc/Fch: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/Proc/Fch/Common: No such file or directory [-Werror=missing-include-dirs] Change-Id: I745f4fc421c91c413fe0d3155d3494ed9704eeb6 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* vendorcode/intel/fsp: Expose DisableDynamicTccoldHandshakeBora Guvendik2023-02-031-2/+4
| | | | | | | | | | | | | | | | | Expose DisableDynamicTccoldHandshake in header so that coreboot can disable it. BUG=b:221461379 BRANCH=firmware-brya-14505.B TEST=Boot to OS, check UPD value in debug FSP build. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I0d953f37a2f0dac58fd339e3fe0dc847d5e6d892 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72693 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vendorcode: Add VariableFormat.hPatrick Rudolph2023-01-313-0/+444
| | | | | | | | | | | | | | Add the EDK2 variable format header in order to access the SPI flash variable store. https://github.com/tianocore/edk2/blob/edk2-stable202005/MdeModulePkg/Include/Guid/VariableFormat.h Commit Hash: 9d510e61fceee7b92955ef9a3c20343752d8ce3f Change-Id: Ibe44925555a7d1d2361dd48c0325b840bd68e0ca Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61959 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vendorcode/intel/fsp/fsp2_0: add SPR-SP FSP header filesJonathan Zhang2023-01-2922-0/+3918
| | | | | | | | | | | | | | | Intel Sapphire Rapids Scalable Processor was product launched on Jan. 10, 2023. Add the FSP/HOB header files corresponding to 2022 ww43 git tag EGLSTRM.0.RPB.0090.D.03. Change-Id: I818da37c10f40045d98a9f73e82034c3fe6459e2 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71948 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* vc/intel/fsp/mtl: Update header files from 2431_80 to 2473_86Kulkarni, Srinivas2023-01-242-526/+518
| | | | | | | | | | | | | | | | | | | | | | | Update header files for FSP for Meteor Lake platform to version 2473_86, previous version being 2431_80. FSPM: 1. Removed deprecated UPD PcieMultipleSegmentEnabled 2. Address offset changes FSPS: 1. Removed deprecated UPD ForcMebxSyncUp 2. Address offset changes BUG=b:261150757 Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.corp-partner.google.com> Change-Id: Ie396ad7ef4da2d1c52d37477bbb0815d2d650841 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
* vc/siemens/hwilib: Use 3rd person singular in commentPaul Menzel2023-01-181-1/+1
| | | | | | | | Change-Id: I1d9d123d2a29178541ab24c70ba529f6bfa2b6c8 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* vc/siemens/hwilib: Rename 'maxlen' to 'dstsize'Werner Zeh2023-01-182-15/+13
| | | | | | | | | | | | | | | | | | | | | The parameter 'maxlen' can be a bit confusing as it actually is referring to the size of the destination memory block where the requested parameter is stored to. Rename it to 'dstsize' and change the type to size_t to be more clear here. In addition, add a comment line for this parameter in the description of the function 'hwilib_get_field()'. This patch has no impact to the generated binary (checked with timeless build). Change-Id: I572dc0f3ff3d0c177d608332a88991396b82c2fd Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72045 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
* vc/siemens/hwilib: Fix coding styleWerner Zeh2023-01-182-6/+6
| | | | | | | | | | | | As per the code style there is no space before the opening brace of a function declaration. Delete the space in hwilib.c and hwilib.h. Change-Id: Ie122ccd2dbae97f595463a097826d3415718a8bc Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72044 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* treewide: Fix old-style declarationsElyes Haouas2023-01-171-6/+6
| | | | | | | | | | | Replace old style declaration "const static" with "static const". This to enable "Wold-style-declaration" command option. Change-Id: I757632befed1854f422daaf4dfea58281b16e2f5 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* soc/amd/mendocino: PSP_INCLUDES_HSPKarthikeyan Ramasubramanian2023-01-152-18/+0
| | | | | | | | | | | | | | | Select HSP config to indicate that the SoC includes Hardware Security Processor. This will allow PSP verstage to get and report the HSP state. BUG=None TEST=Build Skyrim BIOS image and boot to ChromeOS on Skyrim. Verify that HSP is reported during the boot sequence. Change-Id: I22446c2bd6202529367da040c09449e6b26f9d7a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* vc/amd/*,soc/amd/*: Add SVC call to get HSP Secure StateKarthikeyan Ramasubramanian2023-01-151-0/+10
| | | | | | | | | | | | | | | | Add an SVC call to get the state of Hardware Security Processor (HSP) in AMD SoCs. This SVC call will be used from PSP verstage to get and report HSP state. BUG=b:198711349 TEST=Build Skyrim BIOS image and boot to OS. Ensure that the HSP state is read and reported in the firmware logs. Change-Id: I7fe3363d308a80cc09e6bdadd8d0bb1d67f7d2bf Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71207 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP RPL.3503.00Bora Guvendik2023-01-132-171/+175
| | | | | | | | | | | | | | | | The headers added are generated as per FSP v3503.00 BUG=b:261159242 BRANCH=firmware-brya-14505.B TEST=Boot to OS Cq-Depend: chrome-internal:5318308, chrome-internal:5318129 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I050c0f81dce1cfc5ef64406e75d9823352564836 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71758 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
* vc/siemens/hwilib/Makefile.inc: Fix "No such file or directory" errorElyes Haouas2023-01-132-2/+2
| | | | | | | | | | | | Fix: cc1: error: src/vendorcode/siemens/hwilib: No such file or directory [-Werror=missing-include-dirs] Change-Id: I0e805ead90dddbee3ba3577d119e465f669231ba Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* vc/eltan/security/Makefile.inc: Remove path to non-existent directoryElyes Haouas2023-01-121-1/+0
| | | | | | | | | | | | Fix: cc1: error: ../../src/vendorcode/eltan/security/include: No such file or directory [-Werror=missing-include-dirs] Change-Id: I806b106c641d0d93ed18c87cf6d863c1cce04b03 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71298 Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* soc/amd: Change Morgana codename to PhoenixMartin Roth2023-01-126-6/+6
| | | | | | | | | | | | | | | | | | | | | | | Now that the next generation of APUs is officially announced, we can unmask morgana. The chip formerly known as Morgana is actually Phoenix. Surprise! This patch just changes the name across the entire codebase. Note that the fw.cfg file will stay pointing to the 3rdparty/amd_blobs/morgana/psp directory until the amd_blobs_repo is updated. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: Ie9492a30ae9ff9cd7e15e0f2d239c32190ad4956 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71731 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* chromeos/cr50_enable_update.c: Clear EC AP_IDLE flagDerek Huang2023-01-101-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | When AP boots up after Cr50 firmware update and reboot, AP finds that Cr50 reset is required for Cr50 to pick the new firmware so it trigger Cr50 reset and power off the system, AP expects system will power on automatically after Cr50 reset. However this is not the case for Chromebox, Chromebox EC set AP_IDLE flag when system is shutting down, when AP_IDLE flag is set in EC, the system stays at S5/G3 and wait for power button presssend. It cause an issue in factory that the operator needs to press power button to power on the DUT after Cr50 firmware update. This patch sends EC command to direct EC to clear AP_IDLE flag after AP shutdown so AP can boot up when Cr50 reset. BUG=b:261119366 BRANCH=firmware-brya-14505.B TEST=DUT boots up after Cr50 firmware update in factory test flow Change-Id: If97ffbe65f4783f17f4747a87b0bf89a2b021a3b Signed-off-by: Derek Huang <derekhuang@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70773 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vc/google: Add and use POST_CODE_CLEAR definitionMartin Roth2023-01-071-1/+2
| | | | | | | | | | | The CR50 code clears the post code value. Add this as a #define. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If3b73a3159ac8ac9ab08c6ff705b0ca289ab453c Reviewed-on: https://review.coreboot.org/c/coreboot/+/71592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* soc/amd/mendocino: Hook up UPD dxio_tx_vboost_enable for PCIe optimizationChris.Wang2023-01-041-1/+2
| | | | | | | | | | | | | | | | | | Add the UPD dxio_tx_vboost_enable for PCIe optimization. It will impact the PCIe signal integrity, need to double-confirm the SI result after enabling this setting. BUG=b:259622787 BRANCH=none TEST=confirm the setting has been set correspondingly with checking the FSP log. Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I05ae5b3091219e0cb1fe469c929fad6a725db678 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71562 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vc/amd/pi/00670F00/Makefile.inc: Remove path to non-existent directoryElyes Haouas2023-01-031-1/+0
| | | | | | | | | | | | | | | | | | | | | Fix: CC romstage/mainboard/amd/pademelon/static.o cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs] CC romstage/mainboard/amd/gardenia/static.o cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs] CC romstage/mainboard/google/kahlee/static.o cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs] CC romstage/mainboard/google/kahlee/static.o cc1: error: src/vendorcode/amd/pi/00670F00/Lib: No such file or directory [-Werror=missing-include-dirs] Change-Id: I038f87f564ed0415035d92bf0d79a9f8ae2227a4 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* tree/acpi: Replace constant "Zero" with actual numberFelix Singer2022-12-271-5/+5
| | | | | | | | | Change-Id: I5a3e3506415f424bf0fdd48fc449520a76622af5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71525 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-16 02:43:57 +0000