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* treewide: convert to %#x hex printsJon Murphy2023-09-285-19/+19
| | | | | | | | | | | | | | | Convert hex print values to use the %#x qualifier to print 0x{value}. BUG=b:296439237 TEST=build and boot to Skyrim BRANCH=None Change-Id: I0d1ac4b920530635fb758c5165a6a99c11b414c8 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78183 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* treewide: Adopt TCG standard namingJon Murphy2023-09-253-14/+14
| | | | | | | | | | | | | | Adopt TCG standard naming and definitions for TPM Return codes. BUG=b:296439237 TEST=Build and boot to OS on skyrim BRANCH=None Change-Id: I60755723262ec205a4c134948b0250aac4974d35 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77665 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vc/intel/fsp/mtl: Update header files from 3323.84 to MTL.3323.86Subrata Banik2023-09-231-46/+74
| | | | | | | | | | | | | | | | | | | | | | | Update header files for FSP for Meteor Lake platform to version 3323.86, previous version being 3323.84. FSPM: 1. Added new UPDs - AcLoadline - DcLoadline - LowerBasicMemTestSize 2. Address offset changes BUG=b:301441204 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I6c2f7f588874b37c52e3926c02e381ceff14f5af Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78065 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
* drivers/tpm: Make temp test value naming consistentJon Murphy2023-09-184-77/+77
| | | | | | | | | | | | | | | | Make naming convention consistent across all functions return values. BUG=b:296439237 TEST=Boot to OS on Skyrim BRANCH=None Change-Id: If86805b39048800276ab90b7687644ec2a0d4bee Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77536 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* vc/intel/raptorlake: Add the FSP v4301.01 headersSean Rhodes2023-09-1510-0/+8886
| | | | | | | | | | | | | | | | Move the existing FSP 4221.00 headers for Raptor Lake to a subdirectory called 4221.00_google, and select this if the vendor is Google. Add the standard FSP 4301.01 headers to a separate directory, from Intel download #686654, and select this for all other vendors. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Icd99bdee1eeac70dfcaca3d07150d3de6bb83d81 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77101 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* chromeos/cse_board_reset.c: Clear EC AP_IDLE flagDerek Huang2023-09-141-0/+3
| | | | | | | | | | | | | | | | | | | | | | When CSE jumps between RO and RW, it triggers global reset so the AP goes down to S5 and back to S0. For Chromebox, when AP goes down to S5 EC set AP_IDLE flag. This cause an issue to warm reset the Chromebox device when it is in recovery mode and powered by USB-C adapter. This patch allows AP to direct EC to clear AP_IDLE flag before trigger reset. BUG=b:296173534 BRANCH=firmware-dedede-136-6.B TEST=Chromebox DUT which is powered by USB-C adapter boots up after warm reset in recovery mode Change-Id: Ib0002c1b8313c6f25d2b8767c60639aed8a4f904 Signed-off-by: Derek Huang <derekhuang@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77632 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daisuke Nojiri <dnojiri@google.com>
* vc/google/chromeos: Move clear_ec_ap_idle() to common codeDerek Huang2023-09-141-14/+2
| | | | | | | | | | | | | | | | Previously the clear_ec_ap_idle() is implemented in cr50_enable_update.c and be called in the file. Move it to common code so that it can be called in cse_board_reset.c TEST=emerge-brask coreboot Change-Id: I2dbe41b01e70f7259f75d967e6df694a3e0fac23 Signed-off-by: Derek Huang <derekhuang@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77631 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* vendorcode/eltan/security: update attribute useJon Murphy2023-09-081-4/+4
| | | | | | | | | | | | | | Update the use of __attribute__((weak)) to the preferred __weak BUG=None TEST=Builds BRANCH=None Change-Id: I75a0e7c03e537be2d38b7f9c6b81eafbb5fb8018 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* vc/intel/fsp2/alderlake_n: Drop unused header filesFelix Singer2023-09-085-7655/+0
| | | | | | | | Change-Id: I870fa65ff05cf5907d62b3af1b2f9c4334b62603 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77260 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vc/intel/fsp/mtl: Update header files from 3292.83 to 3323.84Subrata Banik2023-09-012-7/+10
| | | | | | | | | | | | | | | | | | | | Update header files for FSP for Meteor Lake platform from 3292.83 to 3323.84. The patch changess only a few spacing alignment for FSP-M header and added few PPR (Post Package Repair) related variable for MemInfoHob header. BUG=b:297965979 TEST=Able to build and boot google/rex. Change-Id: I65c6e05256a2ae9516449dbce62affd040cb0e56 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77561 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vc/amd/pi: Add SPDX headers to all files that don't have themMartin Roth2023-08-2644-0/+89
| | | | | | | | | | | | | | | | License classifiers are much better about classifying files with SPDX headers than they are at classifying the general text licenses due to minor variations in the text. To help with classification, add the SPDX headers to the files. To see the current state of coreboot's licensing, see: https://coreboot.org/fossology/ Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If490f6705e7862d9ad02c925104113b355434101 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* vendorcode/intel/edk2: Use C99 flexible arraysElyes Haouas2023-08-2613-33/+33
| | | | | | | | | | | | | | Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: If093dc08c70c521cbef96ac5b5a7a46b37169bcd Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* vc/intel: Remove unnecessary Kconfig optionsMartin Roth2023-08-261-4/+4
| | | | | | | | | | | | | | These Kconfig options were being used basically as #define statements, which is unnecessary. This isn't a good use of Kconfig options and would be better just as #defines if actually needed. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If987b50d8ec3bb2ab99096e5e3c325e4d90a67a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* vc/siemens: Only add the include path for hwlib when neededMartin Roth2023-08-262-2/+2
| | | | | | | | | | | | | | | | This patch moves the line adding hwlib to the include path to the inner makefile so that it doesn't get added to every build, but only when CONFIG_USE_SIEMENS_HWILIB=y Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id668b76366a554efff560cec746e637487ebdbf4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77417 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vc/amd: Only pull in Makefiles & dirs that are neededMartin Roth2023-08-262-2/+6
| | | | | | | | | | | | | This keeps the vc/amd/pi & pi/00670F00 Makefiles from getting pulled into the build when they aren't needed. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If600c78c2ba74dd03cf493586dae037b96b7d623 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* vc/eltan: Only pull in vc/eltan/security Makefile when enabledMartin Roth2023-08-261-1/+1
| | | | | | | | | | | | | This change tells the build to only pull vc/eltan/security/Makefile.inc into the overall build when USE_VENDORCODE_ELTAN is enabled in Kconfig. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I1e462d8cc21c44716463c41cab598588cf4a22c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77418 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* vc/intel/fsp2_0: Add a copy of ADL-S IOT FSP MemInfoHob.h for RPL-S IOTMichał Żygowski2023-08-211-0/+315
| | | | | | | | | | | | | | | | | | Similar situation happened last year when IoT FSP for ADL-S came out before the Client FSP variant: https://github.com/intel/FSP/issues/83 It seems IoT FSP publishes the MemInfoHob.h file much later due to legal reasons. Hack the missing file to get the builds using RPL-S IoT FSP from repo working properly. This change could be merged, subject for later revert (when the header file is published). Change-Id: Iec35db4573a3c3d011e4c1edf1c82a5c34438695 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76324 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* vc/intel/fsp/mtl: Add PsysPmax FspmUpdKilari Raasi2023-08-211-46/+56
| | | | | | | | | | | | | | | | | | | | This patch adds the PsysPmax Upd to FSPM header file. FSPM: 1. Add 'PsysPmax' UPD 2. Address offset changes BUG=b:295126631 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I892b8c2d75e58a42d3f85006237827da01426ea7 Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77244 Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* vc/intel/fsp/mtl: Update header files from 3223.80 to 3292.83Dinesh Gehlot2023-08-182-6/+4
| | | | | | | | | | | | | | | | | Update header files for FSP for Meteor Lake platform to version 3292.83, previous version being 3223.80. The patch doesn't include any function changes, only a few comments and headers have been changed. BUG=b:295126631 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I27f88732bfafd4732ea39bf9c54e18341dd26cf9 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* vendorcode/fsp: Rename GLK to Gemini Lake to match other SOCsSean Rhodes2023-08-166-0/+0
| | | | | | | | | Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic559b78e6444acec36d437fe3c139b692a3f4d0a Reviewed-on: https://review.coreboot.org/c/coreboot/+/77126 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* mb/facebook/fbg1701: Add config to additional listFrans Hendriks2023-08-091-0/+1
| | | | | | | | | | | | | | | | | ´config´ is removed from measure list (CB:74750) Add 'config' to ram_stage_additional_list[] to have it measured and verified. BUG=NA TEST=boot and verify coreboot logs on facebook FBG1701 Change-Id: Id4119bc3a01e11f14a091facf81964d1a71092c1 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* vendorcode/cavium: Use C99 flexible arraysElyes Haouas2023-08-082-2/+2
| | | | | | | | | | | | | Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I19c029968584fedbb6749e66c7ea2f74a7d580f4 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76811 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* soc/amd/phoenix: Add SVC call to inject v2 hash tablesKarthikeyan Ramasubramanian2023-08-041-3/+26
| | | | | | | | | | | | | | | | | | | On mainboards using Phoenix SoC with PSP verstage enabled, to accommodate growing number of PSP binaries, multiple smaller hash tables are introduced. Also some hash tables are in V2 format identifying the concerned PSP binaries using UUID. Add SVC calls to support multiple hash tables with different versions. BUG=b:277292697 TEST=Build and boot to OS in Myst with PSP verstage enabled. Ensure that all the hash tables are injected successfully. Ensure that PSP validated all the signed PSP binaries using the injected hash tables successfully. Change-Id: I64e1b1af55cb95067403e89da4fb31bec704cd4f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76588 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vendorcode/google: Use C99 flexible arraysElyes Haouas2023-08-011-1/+1
| | | | | | | | | | | | | Use C99 flexible arrays instead of older style of one-element or zero-length arrays. It allows the compiler to generate errors when the flexible array does not occur at the end in the structure. Change-Id: I81ae8acb0365af102e513b3d7cfa1a824636eb06 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76812 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vendorcode/amd/fsp/common: Refactor dmi_info.hKonrad Adamczyk2023-07-219-737/+89
| | | | | | | | | | | | | | | | | | | | SoC family is able to provide SoC-specific information via amd/fsp/<soc_family>/soc_dmi_info.h. Use common amd/fsp/common/dmi_info.h for all AMD platforms. This way, duplicated dmi_info.h files in vendorcode/amd/fsp/<soc_family>/ can be removed. BUG=b:288520486 TEST=Dump `dmidecode -t 17`. Change-Id: I5e0109af51b78360f7038b20a2975aceb721a7d5 Signed-off-by: Konrad Adamczyk <konrada@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76107 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vc/amd/fsp/phoenix/FspmUpd: drop eMMC-related UPDsFelix Held2023-07-141-7/+2
| | | | | | | | | | | | | Phoenix doesn't have an eMMC controller and those UPDs were carried over from Picasso. The SoC's fsp_m_params.c didn't write to any of those fields, so this doesn't change any behavior. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie3640c1493a92c1effba3ce42103d022bd8399ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/76450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* vc/amd/fsp/glinda/platform_descriptors: add dxio_port_param_type TODOFelix Held2023-07-141-0/+1
| | | | | | | | | | | | The dxio_port_param_type enum was copied over from Cezanne, but the enum on the AGESA/FSP side changed between the generations. Add a TODO as a reminder that this needs to be updated. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8063ab00a508b045265bab73197c8ca117622800 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76448 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vc/amd/fsp/*/platform_descriptor: add dxio_link_hotplug_type enumFelix Held2023-07-145-5/+55
| | | | | | | | | | | | Add the dxio_link_hotplug_type enum definition for the link_hotplug field in the DXIO descriptor struct. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ieeb3e3edaed2c689707edc4df7d25c777005fde2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* vc/amd/fsp/phoenix/platform_descriptors: fix dxio_port_param_type enumFelix Held2023-07-141-4/+45
| | | | | | | | | | | | | The dxio_port_param_type enum was copied over from Cezanne to Mendocino to Phoenix, but the enum on the AGESA/FSP side changed between the generations. Update the definition to match the definition used in the Phoenix FSP. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3c87fdc8bf0849d797c2af74c1d1495c7d85019f Reviewed-on: https://review.coreboot.org/c/coreboot/+/76447 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vc/amd/fsp/mendocino/platform_descriptors: fix dxio_port_param_type enumFelix Held2023-07-141-1/+32
| | | | | | | | | | | | The dxio_port_param_type enum was copied over from Cezanne to Mendocino, but the enum on the AGESA/FSP side changed between the two generations. Update the definition to match the definition used in the Mendocino FSP. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie4c4d7e4e3eaf7af9a43007363135412633c7440 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76446 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vc/amd/fsp/*/platform_descriptor: drop SoC name from DDI commentFelix Held2023-07-145-5/+5
| | | | | | | | | | | | | The file for Mendocino and Phoenix still used Cezanne in the comment and from the file it's already clear to which SoC generation this belongs, so just drop the SoC name from the comment. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I73e8b01e46904578226bb64e5e4659016c491880 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76440 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vc/intel/fsp/mtl: Update the MemInfoHob header to FSP version 3251.81Subrata Banik2023-07-141-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates the MemInfoHob header file as per Meteor Lake version 3251.81. Changes include: 1. Drop DimmDFE structure variable 2. Drop unused macro MAX_COPY_DIMM_DFE_TAPS BUG=b:290898626 TEST=Able to build and boot google/rex. w/o this patch: cbmem -c -1 | grep DIMM [ERROR] No DIMMs found w/ this patch: cbmem -c -1 | grep DIMM [DEBUG]  8 DIMMs found Change-Id: I8eed410831399bb4835244f48c14d5ed9e701e68 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76433 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vc/amd/phoenix/platform_descriptor: clarify link_compliance_mode commentFelix Held2023-07-141-1/+1
| | | | | | | | | | | | | | When set to 1, the link_compliance_mode element of the DXIO port descriptor will cause the corresponding PCIe port to not be trained but to output a compliance testing pattern instead. Update the comment to point out that this is only a testing mode. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaabb16c51a0c08391cd2d63b8064c524a748ccb8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76441 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP RPL.4221.00Bora Guvendik2023-07-132-102/+139
| | | | | | | | | | | | | | | The headers added are generated as per FSP v4221.00 BUG=b:290038558 TEST=Boot to OS Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I23f6e1e4baa39883475cd93fa6aabcec4e7152cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/76147 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* vc/intel/fsp/mtl: Update header files from 3194_81 to 3223.80Kilari Raasi2023-07-062-29/+66
| | | | | | | | | | | | | | | | | | | | | | Update header files for FSP for Meteor Lake platform to version 3223_80, previous version being 3194_81. FSPM: 1. Add 'ROWHAMMER','RhSelect','McRefreshRate','Lfsr0Mask','Lfsr1Mask' UPDs 2. Add 'TmeExcludeBase','TmeExcludeSize','GenerateNewTmeKey' UPDs 3. Address offset changes BUG=b:287890130 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I4b8d0a3a87be7dc0d899298eb8e4e48905090e71 Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75916 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* Makefile.inc: don't add fmap_config.h dependency twiceFelix Held2023-06-231-5/+0
| | | | | | | | | | | | | | | Commit d054bbd4f1ba ("Makefile.inc: fix multiple jobs build issue") added a dependency on $(obj)/fmap_config.h to all .c source files in all stages, so it's not needed any more to add it as a dependency to files that include fmap_config.h. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7b62917f32ae9f51f079b243a606e5db07ca9099 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76002 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* commonlib/console/post_code.h: Change post code prefix to POSTCODElilacious2023-06-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The prefix POSTCODE makes it clear that the macro is a post code. Hence, replace related macros starting with POST to POSTCODE and also replace every instance the macros are invoked with the new name. The files was changed by running the following bash script from the top level directory. sed -i'' '30,${s/#define POST/#define POSTCODE/g;}' \ src/commonlib/include/commonlib/console/post_codes.h; myArray=`grep -e "^#define POSTCODE_" \ src/commonlib/include/commonlib/console/post_codes.h | \ grep -v "POST_CODES_H" | tr '\t' ' ' | cut -d ' ' -f 2`; for str in ${myArray[@]}; do splitstr=`echo $str | cut -d '_' -f2-` grep -r POST_$splitstr src | \ cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g"; grep -r "POST_$splitstr" util/cbfstool | \ cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g"; done Change-Id: I25db79fa15f032c08678f66d86c10c928b7de9b8 Signed-off-by: lilacious <yuchenhe126@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* vc/amd/fps/phoenix/platform_descriptors: drop logical-physical mappingFelix Held2023-06-221-12/+3
| | | | | | | | | | | | | | | | | For Phoenix the lane numbers in the DXIO descriptor match the ones in the schematic, so remove the corresponding text and the table from the comment on the fsp_dxio_descriptor struct. Since there's no logical to physical lane number remapping needed for the lanes in the Phoenix DXIO descriptors, drop the 'logical' from the start_logical_lane and end_logical_lane fields in the DXIO descriptor and rename those to start_lane and end_lane. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I94664fd9d3807370b73f9fae8645d444e5faf7b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* vc/intel/edk2: Remove edk2-stable202111 supportRonak Kanabar2023-06-17584-237964/+0
| | | | | | | | | | | | | | This patch removes the support for edk2-stable202111 as MTL has migrated to edk2-stable202302, and no other platform is utilizing edk2-stable202111. The support for edk2-stable202111 is no longer necessary. Change-Id: Ide1864e0a42a4c0a81c3c94b1b1254f8fad062af Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75817 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vendorcode/intel: Add edk2-stable202302 supportRonak Kanabar2023-06-16630-0/+245421
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | edk2-stable202111 is older release of edk2. MTL FSP uses 202302 Edk2. There are structure definition changes between 202111 and 202302. One of change is in FSP_INFO_HEADER structure. Also, Next Gen Intel SoC needs 202302 Edk2. This patch includes (edk2/edk2-stable202302) all required headers for edk2-stable202302 EDK2 tag from EDK2 github project using below command: git clone -b edk2-stable202302 https://github.com/tianocore/edk2.git commit hash: f80f052277c88a67c55e107b550f504eeea947d3 Only include necessary header files. MdePkg/Include/Base.h was updated to avoid compilation errors through safeguarding definitions for MIN, MAX, NULL, ABS, ARRAY_SIZE. Add UefiCpuPkg/Include Because `MpServices2.h` file is part of `UefiCpuPkg/Include/Ppi/` Add following fixes from edk2-stable202111 060492ecd2 Safe guard enum macro in SmBios.h 2bf9599cf1 Use fixed size struct elements BUG=b:261689642 TEST= select UDK_202302_BINDING Kconfig for MTL, Test Build and boot rex Image Change-Id: I8d4deab0bd1d2c6df28e067894875b80413cd905 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
* soc|vc/amd/phoenix: Prepare for PSP verstageKarthikeyan Ramasubramanian2023-06-141-0/+28
| | | | | | | | | | | | | | | Update all the required sources to lay the ground work to enable PSP verstage. BUG=b:284984667 TEST=Build Myst BIOS image with PSP verstage enabled. Change-Id: I6fbb1f835ac2ad6ff47f843321e1bd380af7ce33 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75584 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* vc/intel/fsp/fsp20/meteorlake: Add VR config entriesSubrata Banik2023-06-141-46/+74
| | | | | | | | | | | | | | | | | | This patch adds UPD entries into the FSP header file to configure VRs (IA, GT and SA). - `IccLimit` : VR Fast Vmode ICC Limit support - `EnableFastVmode` : Enable/Disable VR FastVmode - `CepEnable` : Enable/Disable CEP (Current Excursion Protection BUG=b:286809233 TEST=Able to build google/rex. Change-Id: I477ab7e4c07156759962bd2eab9dff28a0a3f006 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75761 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
* vc/intel/fsp2: Drop Intel Quark FSP headersFelix Singer2023-06-044-436/+0
| | | | | | | | | | | Intel Quark was dropped in commit 531023285e. Thus, drop the remaining FSP headers. Change-Id: Ie3c11c6f68d879b944f7b4ed0fde0ee4aae204b9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* vc/intel/fsp/mtl: Update header files from 3165_81 to 3194_81Kilari Raasi2023-06-042-4/+88
| | | | | | | | | | | | | | | | | | | | | | | | Update header files for FSP for Meteor Lake platform to version 3194_81, previous version being 3165_81. FSPM: 1. Add 'PchPcieRpEnableMask' UPD 2. Address offset changes Add "FspProducerDataHeader.h" file to support MRC version Info BUG=b:284803304 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I43f276e9b8e46edc76dc7749d2a610cfa836a718 Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75519 Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* vc/intel/fsp/fsp20/meteorlake: Add `SaGvWpMask`Subrata Banik2023-05-251-74/+77
| | | | | | | | | | | | | | | | | This patch adds `SaGvWpMask` UPD into the FSP header. This information is required to set the SaGv work endpoint. BUG=b:283746904 TEST=Able to build google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: If39da58c927cc7b28b46063576f8e246ef9596d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75361 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
* vc/amd/pi/amdlib.c: Use native coreboot code over compiler builtinsArthur Heymans2023-05-242-3/+4
| | | | | | | | | | | | | Compiler builtins depend on certain CPU features flags to be passed to the compiler. This may have unwanted side effects as generating code with FPU registers. Instead use native coreboot code. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I4e92d103fa3a6c7a56e813a583b3262676969669 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* src/vc/intel/fsp/fsp2_0/sapphirerapids_sp: Update Spr header filesSrinidhi N Kaushik2023-05-2312-302/+326
| | | | | | | | | | | | | | This change updates Intel Copyright License for all header files under Sapphirerapids dir Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ib04988194e5fe9515bea8620318eadff36f92181 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* vc/amd/fsp/phoenix/FspUsb: update USB config struct for Phoenix SoCFelix Held2023-05-181-7/+5
| | | | | | | | | | | | | | | | | Phoenix has one more Type C port and two more USB2 ports which are used as the legacy USB part of the two USB4 ports. The USB struct version numbers have also changed, since it's a newer and incompatible version of that struct. TEST=After changing FSP to not hard-code the USB PHY config, but use the configuration provided by coreboot, and applying this patch, the USB connector on the USB2 port 4 lines works. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If52934595dd612154b97e7b90dbd96243146017a Reviewed-on: https://review.coreboot.org/c/coreboot/+/73379 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vendorcode/mediatek/mt8195: Fix set but unused variablesArthur Heymans2023-05-131-1/+1
| | | | | | | | Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I5738e73f2121e2558831fbaa9c92a2fd0926ad88 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* vendorcode/mediatek/mt8195: More sure ucDoneFlg is initializedArthur Heymans2023-05-131-1/+1
| | | | | | | | | | | One some codepaths ucDoneFlg is not initialized. This fixes a clang warning. Change-Id: I78aa2c711626b24f003f5c95b1c9598eaff7cb1b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-28 02:06:34 +0000