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* soc/intel/denverton_ns: Always enable SpeedStepDmitry Ponamorev2021-10-071-6/+4
* sc7280: Enable UART driverRajesh Patil2021-10-062-0/+13
* sc7280: Enable bootblock compressionRavi Kumar Bokka2021-10-063-0/+13
* ec/google/chromeec: Register USB-C mux operationsDerek Huang2021-10-062-1/+20
* ec/google/chromeec: Update google_chromeec_usb_pd_get_info()Derek Huang2021-10-062-4/+2
* ec/google/chromeec: Add new API for USB-C mux handlingDerek Huang2021-10-062-0/+44
* ec/google/chromeec: Add APIs for USB-C DP ALT modeDerek Huang2021-10-062-0/+54
* ec/google/chromeec: Update some PD and DisplayPort APIsDerek Huang2021-10-062-13/+29
* ec/google/chromeec: Update google_chromeec_usb_pd_control()Derek Huang2021-10-062-3/+5
* include/device: Generic interface for USB-C mux operationsDerek Huang2021-10-061-0/+69
* soc/intel/alderlake: Skip setting D0I3 bit for HECI devicesSubrata Banik2021-10-061-0/+2
* soc/intel/alderlake: Perform `heci_finalize` prior to booting to OSSubrata Banik2021-10-061-0/+19
* soc/intel/common: Helper function to check CSE device `devfn` statusSubrata Banik2021-10-062-6/+18
* soc/intel/common/../cse: Allow D0i3 enable/disable for all CSE devicesSubrata Banik2021-10-063-41/+41
* lib/thread: Remove thread stack alignment requirementRaul E Rangel2021-10-051-16/+5
* Revert "soc/amd/cezanne: Disable Co-op multitasking"Raul E Rangel2021-10-051-0/+3
* lib/thread: Switch to using CPU_INFO_V2Raul E Rangel2021-10-052-23/+6
* arch/x86,cpu/x86: Introduce new method for accessing cpu_infoRaul E Rangel2021-10-058-3/+186
* drivers/intel/fsp2_0: don't force-use `python2`Michael Niewöhner2021-10-051-1/+1
* src/soc to src/superio: Fix spelling errorsMartin Roth2021-10-0575-91/+91
* src/mainboard to src/security: Fix spelling errorsMartin Roth2021-10-0558-64/+64
* src/acpi to src/lib: Fix spelling errorsMartin Roth2021-10-0552-68/+68
* driver/intel/pmc_mux/conn: Add type-c port info to cbmemNick Vaccaro2021-10-051-0/+64
* mb/google/trogdor: Add new vaviant quackingstickSheng-Liang Pan2021-10-042-2/+7
* soc/intel/adl: Drop SGPM, RGPM and EGPM methodsMeera Ravindranath2021-10-041-41/+0
* mb/*/brya/variants/brask: Enable dynamic GPIO PMMeera Ravindranath2021-10-041-11/+0
* mb/intel/adlrvp{p,m}: Enable dynamic GPIO PMMeera Ravindranath2021-10-042-19/+0
* mb/google/brya: Enable DDR4 SODIMM for braskDavid Wu2021-10-049-12/+68
* src/soc/intel/alderlake: Add PsysPmax settingRyan Lin2021-10-042-0/+10
* driver/intel/pmc_mux/conn: Move typec_orientation enum to coreboot_tables.hNick Vaccaro2021-10-043-14/+19
* coreboot tables: Add type-c port info to coreboot tableNick Vaccaro2021-10-043-1/+22
* lib/hardwaremain: change type of "complete" element in boot_state structFelix Held2021-10-041-3/+3
* lib/hardwaremain: add missing types.h includeFelix Held2021-10-041-0/+1
* mb/google/brya/variants/kano: Correct MIPI camera infoLai, Jim2021-10-041-3/+3
* soc/intel/common: round PM Timer emulation frequency multiplierMichael Niewöhner2021-10-021-1/+2
* soc/mediatek: add debug dump for ltiming and clock_divRex-BC Chen2021-10-023-0/+21
* soc/mediatek: Fix I2C failures by adjusting AC timing and bus speedDaolong Zhu2021-10-027-69/+336
* soc/intel/common/../cse: Avoid caching of CSE BARSubrata Banik2021-10-021-42/+17
* soc/intel/common/../cse: Append `_MS` with CSE_DELAY_BOOT_TO_RO macroSubrata Banik2021-10-021-4/+3
* mb/google/dedede/var/bugzzy: Update device treeSeunghwan Kim2021-10-011-12/+212
* soc/tigerlake: Make IO decode / enable register configurableSean Rhodes2021-10-012-3/+20
* mb/google/brask/var/brask: Configure GPIOs according to schematicsDavid Wu2021-10-012-0/+68
* soc/intel/alderlake: add power limits for Alder Lake-M 282 SKUSumeet Pawnikar2021-10-012-3/+11
* mb/intel/adlrvp: set PL4 value dynamically for thermalSumeet Pawnikar2021-10-012-8/+14
* mb/google/brya: move MILLIWATTS_TO_WATTS macro in header fileSumeet Pawnikar2021-10-012-2/+2
* mb/intel/adlrvp: set power limits dynamically for thermalSumeet Pawnikar2021-10-012-6/+11
* acpi/acpigen_dptf: Add TPCH participant for dptfSumeet Pawnikar2021-10-012-0/+3
* soc/intel/common: Add PMC IPC commands for FIVR controlSumeet Pawnikar2021-10-011-2/+10
* mb/google/brask: Correct SSD power sequenceEric Lai2021-10-011-2/+11
* mb/google/brya/var/felwinter: Correct SSD power sequenceEric Lai2021-10-011-0/+15
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