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* Kconfig whitespace fixesMartin Roth2015-04-2844-164/+164
| | | | | | | | | | trivial whitespace fixes. Mostly changing leading spaces to tabs. Change-Id: I0bdfe2059b90725e64adfc0bdde785b4e406969d Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/10000 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* fsp platforms: consolidate FspNotify callsMartin Roth2015-04-284-65/+29
| | | | | | | | | | | Consolidate the FspNotify calls into the FSP driver directory, using BOOT_STATE_INIT_ENTRY to set up the call times. Change-Id: I184ab234ebb9dcdeb8eece1537c12d03f227c25e Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/9780 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Fix some minor Kconfig issuesMartin Roth2015-04-286-34/+3
| | | | | | | | | | | | | | | | | - Remove Kconfig files that are no longer used: src/vencorcode/Kconfig src/soc/marvell/Kconfig - Fix the drivers/sil/Kconfig to point to drivers/sil/3114 which had the same code. - Make sure all Kconfig files have linefeeds at the end. This can cause problems, although it wasn't in this case. - Include cpu/intel/model_65x/Kconfig which was not being included. Change-Id: Ia57a1e0433e302fa9be557525dc966cae57059c9 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/9998 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Makefile x86 SMM: Move smm_wrap recipesKyösti Mälkki2015-04-281-16/+15
| | | | | | | | | | | This is not used together with SMM_MODULES. Change-Id: I52621787cfa5a9e3863c150ce64f62aceb423eb4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10014 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* arm: guard verstage rulesAaron Durbin2015-04-281-0/+4
| | | | | | | | | | | | Do not unconditially supply verstage rules for all platforms. Change-Id: Ic0713350aa21a9966fca828211750d25c2b6b71d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9969 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* vboot: remove vboot_helper.cAaron Durbin2015-04-281-168/+0
| | | | | | | | | | | | | This file was moved previously to get it out of the way for easier merging from the chromium repo. It's not used currently so remove it. Change-Id: I8e691623f29ac2218b83bc46f5b4a348e0e1b3ef Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9960 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* boards: remove VBOOT_(REFCODE|RAMSTAGE|ROMSTAGE)_INDEXAaron Durbin2015-04-2821-123/+0
| | | | | | | | | | | | These options will need to just be selected in within the .config files. There's not need in duplicating all these options. Change-Id: I7b670bc59a3b35e39eee4faecaf4aa779d47a3bb Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9959 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* chromeos: remove VBOOT2_VERIFY_FIRMWARE optionAaron Durbin2015-04-2814-51/+25
| | | | | | | | | | | There's no need to have the VBOOT2_VERIFY_FIRMWARE distinction because it's the only game in town. Change-Id: I82aab665934c27829e1a04115bf499ae527a91aa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9958 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* vboot: remove vboot1Aaron Durbin2015-04-287-797/+25
| | | | | | | | | | | | In preparation for moving to vboot2 for all verified boot paths bring over Kconfig options to the common area from vboot1. Also remove vboot1 directory entirely. Change-Id: Iccc4b570216f834886618f0ba5f2e1dd6c01db4b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9957 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* marvell/bg4cd: merge verstage into bootblockDaisuke Nojiri2015-04-286-13/+104
| | | | | | | | | | | | | | | | | | | | | | If verified boot is enabled, merge verstage into bootblock. This also requires custom bootblock code to actually call into verstage. [pg: modified to match upstream] BUG=chrome-os-partner:32631 BRANCH=ToT TEST=booted on cosmos development board. Change-Id: I53251aac966ee15da24232c23fefa636de8b253b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2b8ada263017b46afa755b5acb759574184dba06 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: Ia0e1236357aa32bf553fb8cc98f3a8d29de17f45 Original-Reviewed-on: https://chromium-review.googlesource.com/229795 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/10008 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* vboot2: Allow merging verstage into bootblockPatrick Georgi2015-04-282-0/+14
| | | | | | | | Change-Id: I31cd7f84db8b7176c8854f33421aab5c176cd5ce Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10007 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* vboot2: Always enable timestampsPatrick Georgi2015-04-281-0/+1
| | | | | | | | | | The vboot2 code requires them. Change-Id: I9afaf9b373297b0eebce9ffd7cc05766dee7d6fd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10006 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* vboot2: get rid of global variable that is used locally and only oncePatrick Georgi2015-04-281-2/+1
| | | | | | | | Change-Id: Iaf6d6a8857451fb16916aaae97a6fd5c51bc8cc4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10005 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* vboot2: Build verstage archive, then use that for building the stagePatrick Georgi2015-04-283-4/+6
| | | | | | | | | | | This slightly streamlines integrating the vboot2 library and prepares for merging verstage and bootblock on selected devices. Change-Id: I2163d1411d0c0c6bf80bce64796e1b6a5a02b802 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10004 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* lib: When used, add timestamp.c to bootblock and verstage, tooPatrick Georgi2015-04-281-0/+2
| | | | | | | | | | | Otherwise it won't build. Change-Id: If9e1435b0dc8bfe220b3a257976e928373fbc9a5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10003 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* arch/arm: Move inclusion of timestamps.c to the right directoryPatrick Georgi2015-04-282-2/+4
| | | | | | | | | | | | Without this, building with COLLECT_TIMESTAMPS fails. Fixes a mistake during upstreaming in commit 0de8820. Change-Id: Ie56bd38649a821f6b22a1e5dee5f50ef397035fe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10002 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* OxPCIe: Fix UART base addressesKyösti Mälkki2015-04-281-6/+2
| | | | | | | | | | | | The offset of 0x2000 was for a configuration with two separate OxPCIe chips. The setup we support is a single chip with 8 UART pors. Change-Id: If4be046a14464af7b90b86aca5464c6b3400dffc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8780 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* intel SMI handlers: Refactor GPI SMI/SCI routingKyösti Mälkki2015-04-2823-317/+167
| | | | | | | | | | | | | Move the GPI interrupt routing selection between SMI/SCI from mainboards to southbridge. There is speculation if this is all just legacy APM stuff that could be removed with a followup. Change-Id: Iab14cf347584513793f417febc47f0559e17f5a5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/7967 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
* x60,t60,x201,macbook21 : Declare GPIs for ECKyösti Mälkki2015-04-284-14/+23
| | | | | | | | | | | | | | For lenovo/x201, this also changes GPI_ROUT (0xb8-0xbb) programming to use GPI1 between SCI/SMI modes, while previous programming was for GPI12. Change-Id: I3ac0feaa1d10c8f0e53a5fa5af72366503bb5d2d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/8656 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* kbuild: automatically include southbridgesStefan Reinauer2015-04-2776-128/+209
| | | | | | | | | | | | | | | | | | | | | | | | | | This change switches all southbridge vendors and southbridges to be autoincluded by Makefile.inc, rather than having to be mentioned explicitly in southbridge/Makefile.inc or in southbridge/<vendor>/Makefile.inc. In order to be able to drop southbridge/amd/Makefile.inc, some scattered source files had to be moved to a southbridge/amd/common directory, in accordance to what we are doing on other architectures already. This means, vendor and southbridge directories are now "drop in", e.g. be placed in the coreboot directory hierarchy without having to modify any higher level coreboot files. The long term plan is to enable out of tree components to be built with a given coreboot version (given that the API did not change). Change-Id: I79bd644a0a3c4e8320c80f8cc7a7f8ffd65d32f2 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/9796 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* arch/arm64: update mmu translation table granule size, logic and macrosJimmy Huang2015-04-272-51/+40
| | | | | | | | | | | | | | | | | | | | | | | 1. change mmu granule size from 64KB to 4KB 2. correct level 1 translation table creation logic 3. automatically calculate granule size related macros BRANCH=none BUG=none TEST=boot to kernel on oak board Change-Id: I9e99a3017033f6870b1735ac8faabb267c7be0a4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2f18c4d5d9902f2830db82720c5543af270a7e3c Original-Change-Id: Ia27a414ab7578d70b00c36f9c063983397ba7927 Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/265603 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Reviewed-on: http://review.coreboot.org/10009 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
* chromeec: ec_mec: Fix misaligned data accessShawn Nematbakhsh2015-04-271-1/+26
| | | | | | | | | | | | | | | | | | | | | | Long auto-increment access cannot be used when our initial address is misaligned or when our terminal address is misaligned on write operations. BUG=chrome-os-partner:38224 TEST=Verify host command functionality on cyan. BRANCH=None Change-Id: Ieba0e8e05dabd44a28c63d5d56a2a634c2d349bf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a7237c8df027ae70a38478846ff3d5ce97543ff1 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Change-Id: Id709ca92cc386f9ea5b2a1139733961e1bc59354 Original-Reviewed-on: https://chromium-review.googlesource.com/266653 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9987 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* storm: enable CBMEM console dumpVadim Bendebury2015-04-271-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables on storm the recently introduced 'console buffer dump on reboot' capability. BRANCH=none BUG=chromium:475347 TEST=generated storm image with serial console disabled and both rw firmware A and B sections corrupted. Programmed the new image on an SP5 device and rebooted it. Observed the device dump cbmem console buffer to the serial output, terminating with VB2:vb2_fail() Need recovery, reason: 0x3 / 0xa Reboot requested (1008000a) Saving nvdata SF: Detected S25FL128S_256K with page size 10000, total 2000000 and the LED ring started flashing indicating recovery mode. Change-Id: Idb50c86f59f393c783ccbc15de8f5564e2a1b38e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0ec88001b152bb9f1d7268b83367131b004816f8 Original-Change-Id: I9345eeb4d375f42fb1e4c617495b63b308ce51d9 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/265295 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9986 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
* Cygnus: add TrustZone functions and set everything non-secure in bootblockCorneliu Doban2015-04-274-99/+643
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | To allow an OS to run in non-secure mode: - Set all peripherals and system components non-secure except SOTP and TZPC. - Set all memory non-secure (ROM, SRAM, DDR, flash). - Enable A9 access to entire M0 address space except M0 ROM. BUG=chrome-os-partner:37533 BRANCH=broadcom-firmware TEST=boot kernel from usb stick Change-Id: I3bbd288863923011ff1413be353ac4b178ffdd07 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6de56bbe73ed8d87ad572da711a193985ee68e3a Original-Signed-off-by: Corneliu Doban <cdoban@broadcom.com> Original-Reviewed-on: https://chrome-internal-review.googlesource.com/212735 Original-Reviewed-by: Daisuke Nojiri <dnojiri@google.com> Original-Commit-Queue: Daisuke Nojiri <dnojiri@google.com> Original-Tested-by: Daisuke Nojiri <dnojiri@google.com> Original-Change-Id: Ibac7de03a72a98fbd95659d0113833049b4871a5 Original-Reviewed-on: https://chromium-review.googlesource.com/266593 Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Original-Trybot-Ready: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: http://review.coreboot.org/9985 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* cbmem: add and use a function to dump console bufferVadim Bendebury2015-04-275-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | The new function can be compiled in only when serial console is disabled. When invoked, this function initializes the serial interface and dumps the contents of the CBMEM console buffer to serial output. BRANCH=none BUG=chromium:475347 TEST=compiled for different platforms with and without serial console enabled. No actual test of this function yet. Change-Id: Ia8d16649dc9d09798fa6970f2cfd893438e00dc5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a38a8254dd788ad188ba2509b9ae117d6f699579 Original-Change-Id: Ib85759a2727e31ba1ca21da7e6c346e434f83b52 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/265293 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9984 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* lib/tlcl: Provide mock implementationYen Lin2015-04-272-0/+142
| | | | | | | | | | | | | | | | | | | | It returns TPM_E_NO_DEVICE for all calls. BRANCH=None BUG=None TEST=manual MOCK_TPM=1 emerge-foster coreboot, and coreboot can boot to kernel Change-Id: Id7e79b58fabeac929b874385064b2417db49a708 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a9a91a65af115657e7317754eda931120750c56d Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Change-Id: I8dcf0db14cf2bc76c67a3bd7f06114e70e08764d Original-Reviewed-on: https://chromium-review.googlesource.com/264946 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9983 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* vboot: #include "fmap.h" for declarationsAaron Durbin2015-04-271-0/+1
| | | | | | | | | | | In the spirit of include what you use actually #include the header necessary for fmap calls. Change-Id: I7acede51d7139234c0520281799dad3a8d33454f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9968 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* intel/fsp_baytrail: Fix default SMM_TSEG_SIZE valueDavid Imhoff2015-04-271-1/+1
| | | | | | | | | | | | | | The value of SMM_TSEG_SIZE was equal to SMM_RESERVED_SIZE. This caused the install_permanent_handler() function to fail. Changed the value to 0x800000, which is already used as default in smm_region_size() in case SMM_TSEG_SIZE is 0. Change-Id: I4ff3568aefd4729a98c1777a2cae2a4715afbc2f Signed-off-by: David Imhoff <dimhoff_devel@xs4all.nl> Reviewed-on: http://review.coreboot.org/9961 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* arm64: save/restore cptr_el3 and cpacr_el1 registersJoseph Lo2015-04-274-2/+23
| | | | | | | | | | | | | | | | | | | | | | CPTR_EL3 and CPACR_EL1 are the registers for controlling the trap level and access right of the FPU/SIMD instructions. Need to save/restore them in every power cycle to keep the settings consistent. BRANCH=none BUG=none TEST=boot on smaug/foster, verify the cpu_on/off is ok as well Change-Id: I96fc0e0d2620e72b6ae2ffe4d073c9328047dc01 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 73e8cc8f25922e7bc218d24fbf4f7c67e15e3057 Original-Change-Id: I51eed07b1bb8f6eb2715622ec5d5c3f80c3c8bdd Original-Signed-off-by: Joseph Lo <josephl@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/266073 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Benson Leung <bleung@chromium.org> Reviewed-on: http://review.coreboot.org/9981 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
* arm64: implement CPU power down sequence as per A57/A53/A72 TRMJoseph Lo2015-04-275-0/+126
| | | | | | | | | | | | | | | | | | | | | | | Implement the individual core powerdown sequence as per Cortex-A57/A53/A72 TRM. Based-on-the-work-by: Varun Wadekar <vwadekar@nvidia.com> BRANCH=none BUG=none TEST=boot on smaug/foster, verify the cpu_on/off is ok as well Change-Id: I4719fcbe86b35f9b448d274e1732da5fc75346b0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b6bdcc12150820dfad28cef3af3d8220847c5d74 Original-Change-Id: I65abab8cda55cfe7a0c424f3175677ed5e3c2a1c Original-Signed-off-by: Joseph Lo <josephl@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/265827 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9980 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
* arm64: introduce data cache ops by set/way to the level specifiedJoseph Lo2015-04-277-60/+184
| | | | | | | | | | | | | | | | | | | | | | | | This patchs introduces level specific data cache maintenance operations to cache_helpers.S. It's derived form ARM trusted firmware repository. Please reference here. https://github.com/ARM-software/arm-trusted-firmware/blob/master/ lib/aarch64/cache_helpers.S BRANCH=none BUG=none TEST=boot on smaug/foster Change-Id: Ib58a6d6f95eb51ce5d80749ff51d9d389b0d1343 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b3d1a16bd0089740f1f2257146c771783beece82 Original-Change-Id: Ifcd1dbcd868331107d0d47af73545a3a159fdff6 Original-Signed-off-by: Joseph Lo <josephl@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/265826 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9979 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
* arm64: perform early setup in secmon tooJoseph Lo2015-04-272-0/+2
| | | | | | | | | | | | | | | | | | | | | Same as commit fe0eac5f416e "arm64: Allow cpu specific early setup", we need the same in secmon too. BRANCH=none BUG=none TEST=boot on smaug/foster Change-Id: I5b1347880306a95f99233db12cb99547bad4aa8c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1f70fd940ff92eb5b8991cd777c2894b7a9633cf Original-Change-Id: Ifce5a6d636051e7a447d055c8e09ed4e29e091c7 Original-Signed-off-by: Joseph Lo <josephl@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/265825 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Benson Leung <bleung@chromium.org> Reviewed-on: http://review.coreboot.org/9978 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
* arm64: Allow cpu specific early setupFurquan Shaikh2015-04-278-1/+134
| | | | | | | | | | | | | | | | | | | | | | | | Call arm64_cpu_early_setup to allow cpu-specific initialization to be performed. Also, add support for setting SMPEN bit for cortex a57 within arm64_cpu_early_setup. BUG=chrome-os-partner:38222 BRANCH=None TEST=Compiles successfully and SMP works for foster Change-Id: Ifa4e6134dbce3ad63046b3dd9b947c3d9134d5e7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fe0eac5f416efcf9f7b05388a17444205a8352c0 Original-Change-Id: I28a05a20e6adf084cd0bf94bdd0c3b492632107c Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/262993 Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9977 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
* driver/intel/fsp: Correct the fastboot data (MRC data) printing lengthYork Yang2015-04-242-2/+2
| | | | | | | | | | | Fastboot data in Intel FSP project is printed by hexdump32() in dword length. So the data length needs to be divided by 4 when printing it. Change-Id: I959d538bd6e60282882dd138045cc730b4bd8159 Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: http://review.coreboot.org/9976 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
* fsp: Move fsp to fsp1_0Marc Jones2015-04-2481-40/+40
| | | | | | | | | | | Prepare for FSP 1.1 integration by moving the FSP to a FSP 1.0 specific directory. See follow-on patches for sharing of common code. Change-Id: Ic58cb4074c65b91d119909132a012876d7ee7b74 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/9970 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* ramstage: don't drop cbmem consoleAaron Durbin2015-04-231-5/+6
| | | | | | | | | | | | | | | | | In commit b0d8f5e9 I moved the call to cbmem_initialize() in the CONFIG_EARLY_CBMEM_INIT case to the very beginning of ramstage. However, that caused an issue in the ordering of the cbmem console driver in that it expects cbmemc_init() to be called prior to cbmemc_reinit(). Therefore, ensure console is called as the first thing even if some time is lost w.r.t. timestamp tracking. Change-Id: I42137d28116e0bccb9235f4e3f394d4fd8b84e37 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9933 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* cbmem_console: fix it for x86Aaron Durbin2015-04-234-24/+24
| | | | | | | | | | | | The Kconfig options pertaining cbmem console in the preram environment no longer make sense with the linker script changes. Remove them and their usage within cbmem_console. Change-Id: Ibf61645ca2331e4851e748e4e7aa5059e1192ed7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9851 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* memlayout: Make sure preram_cbmem_console symbols existPatrick Georgi2015-04-232-0/+4
| | | | | | | | | | | | | This enables its _size variable (a macro) to work even when the console has no location assigned to it in the chip/board's memlayout.ld. Since _size == 0, the code will do the right thing. Change-Id: I6b42ed0c5c3aaa613603680728b61cbdb24c4b61 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9973 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* src/mainboard/*/*/board_info.txt: Added Release year for boardsMathias Friman2015-04-2397-2/+98
| | | | | | | | | | | | | | | To simplify browsing the "Supported hardware" list, I added Release year for the hardware from asus, asrock, gigabyte, msi, via, tyan, intel, lenovo, apple, jetway and hp. Still several models and manufacturers to add information to. This is more of a proof-of-concept. The "Release year" will be shown in the wiki page. Change-Id: I6bc14ed06ac7c6b3c9f054b49f08cb9b3dc47947 Signed-off-by: Mathias Friman <mathias@workplays.se> Reviewed-on: http://review.coreboot.org/9963 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
* AMD Lamar: Add a new AMD FP3 socket mainboardBruce Griffith2015-04-2324-0/+2219
| | | | | | | | | | | | Add a new mainboard based on AMD's Family 15 Model 30 processor. TEST: Lamar will boot DOS, Ubuntu 14.10 and Windows 7. Change-Id: I2f73c396247239d54f978846e8958950697d7464 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/5968 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
* cbmem: switch over to imd-based cbmemAaron Durbin2015-04-225-513/+317
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By design, the imd library still provdes dynamic growth so that feature is consistent. The imd-based cbmem packs small allocations into a larger entry using a tiered imd. The following examples show the reduced fragmentation and reduced memory usage. Before with dynamic cbmem: CBMEM ROOT 0. 023ff000 00001000 aaaabbbb 1. 023fe000 00001000 aaaabbbc 2. 023fd000 00001000 aaaabbbe 3. 023fc000 00001000 aaaacccc 4. 023fa000 00002000 aaaacccd 5. 023f9000 00001000 ROMSTAGE 6. 023f8000 00001000 CONSOLE 7. 023d8000 00020000 COREBOOT 8. 023d6000 00002000 After with tiered imd: IMD ROOT 0. 023ff000 00001000 IMD SMALL 1. 023fe000 00001000 aaaacccc 2. 023fc000 00001060 aaaacccd 3. 023fb000 000007cf CONSOLE 4. 023db000 00020000 COREBOOT 5. 023d9000 00002000 IMD small region: IMD ROOT 0. 023fec00 00000400 aaaabbbb 1. 023febe0 00000020 aaaabbbc 2. 023feba0 00000040 aaaabbbe 3. 023feb20 00000080 ROMSTAGE 4. 023feb00 00000004 Side note: this CL provides a basis for what hoops one needs to jump through when there are not writeable global variables on a particular platform in the early stages. Change-Id: If770246caa64b274819e45a26e100b62b9f8d2db Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9169 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
* elog: enable by default for CHROMEOSPatrick Georgi2015-04-221-0/+1
| | | | | | | | | | | | | | | elog breaks the build if ELOG_FLASH_BASE isn't configured - and CHROMEOS isn't enabled, since with Chrome OS builds, it just uses fmap to find out the base. So it makes sense to enable it on all Chrome OS builds - if the code never uses it, the linker will drop it soon enough. Change-Id: I7ee129fadf75caf15fb9bd32b0acf6f7d9d015d8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/9965 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* google/storm: indicate start of normal boot on LED ringVadim Bendebury2015-04-221-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of switching off the LED ring for the normal boot path, turn it on with the dedicated pattern, indicating that the device firmware has started executing. BRANCH=storm BUG=chrome-os-partner:39044 TEST=program the new firmware on an SP5 device and verify that the new 'normal boot' pattern is displayed in all following scenarios: - power up the device (the pattern shows within the first second) - boot the device to bash prompt and restart. - press the recovery button and reboot the device. Once the LED ring shows the 'recovery button pressed' pattern, release the recovery button. Change-Id: Iedd66d2575ad587af77e35d23efb22a83a92858b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 092358bd17a323d0bd2fec555f43cb587486bbec Original-Change-Id: I24de45326eab83b57bcf16b5598388f81c7d0f00 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/265536 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9923 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* i2c/ww_ring: add a pattern for normal bootVadim Bendebury2015-04-222-1/+88
| | | | | | | | | | | | | | | | | | | | | It became necessary to indicate the beginning of the normal boot process. This patch adds a new pattern, a slow (over 2 seconds) fade in into the 0, 87, 155 color. BRANCH=storm BUG=chrome-os-partner:39044 TEST=tested by the next patch. Change-Id: Idd977688e5aa2cc55fc295072c0766526ae95016 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 577c8bd6f8c69073cfdd7acd4a87e7ae603d48e6 Original-Change-Id: I9aff3f4558e733ff2e47206075533556e400f183 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/265535 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9922 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* google/storm: enable zero page access protection.Deepa Dinamani2015-04-221-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BRANCH=storm BUG=chrome-os-partner:24786 TEST=verified mmu.pagetable.list output for Storm: _______address___________|_physical________________|sec|_d_|_size____|_permissions____________________|_glb|_shr|_pageflags______________________| C:00000000--00000FFF| | | | | | | | | C:00001000--000FFFFF| A:00:00001000--000FFFFF| ns| 00| 00001000| P:readwrite U:readwrite notexec| yes| no | strongly ordered | C:00100000--29FFFFFF| A:00:00100000--29FFFFFF| ns| 00| 00100000| P:readwrite U:readwrite notexec| yes| no | strongly ordered | C:2A000000--2A05FFFF| A:00:2A000000--2A05FFFF| ns| 00| 00001000| P:readwrite U:readwrite exec | yes| no | write-back/no write alloc | C:2A060000--2A0FFFFF| A:00:2A060000--2A0FFFFF| ns| 00| 00001000| P:readwrite U:readwrite notexec| yes| no | strongly ordered | C:2A100000--3FFFFFFF| A:00:2A100000--3FFFFFFF| ns| 00| 00100000| P:readwrite U:readwrite notexec| yes| no | strongly ordered | C:40000000--59FFFFFF| A:00:40000000--59FFFFFF| ns| 00| 00100000| P:readwrite U:readwrite exec | yes| no | write-back/no write alloc | C:5A000000--5A1FFFFF| A:00:5A000000--5A1FFFFF| ns| 00| 00100000| P:readwrite U:readwrite notexec| yes| no | strongly ordered | C:5A200000--7FFFFFFF| A:00:5A200000--7FFFFFFF| ns| 00| 00100000| P:readwrite U:readwrite exec | yes| no | write-back/no write alloc | C:80000000--FFFFFFFF| | | | | | | | | Change-Id: I08a5094b2da9d67244c94984e2da14399e477b01 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f137a589434b09055e6b9d32907e662e6c296502 Original-Change-Id: Ia2deab1cf8f08c4ba5a5b6dbe4c4ebf29c9df480 Original-Signed-off-by: Vikas Das <vdas@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/253801 Original-Tested-by: Deepa Dinamani <deepad@codeaurora.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Deepa Dinamani <deepad@codeaurora.org> Reviewed-on: http://review.coreboot.org/9920 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* i2c/ww_ring: update color definitionsVadim Bendebury2015-04-221-5/+5
| | | | | | | | | | | | | | | | | | | | After testing on a final assembly the PD team adjusted the wipeout request and recovery request modes' colors. BRANCH=storm BUG=none TEST=verified new colors while booting an SP5 device in recovery mode Change-Id: I9bd2dac63b99140573533c2cda8eaa9213478ab1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 41c34a619dc0317af67907f18ee844c71a73d623 Original-Change-Id: Iab84710ebdeed35ddd4a8a163bbb6b8ac9cdb799 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/262602 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9890 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* i2c/ww_ring: change colors for different display modesVadim Bendebury2015-04-221-18/+18
| | | | | | | | | | | | | | | | | | | | | | Modify colors as suggested by product review folks. This is not final, to make it easier to identify RGB locations in the hex dumps, express their values in decimal as opposed to hex. BRANCH=storm BUG=chrome-os-partner:36059 TEST=verified new all three color schemes while pressing the recovery button at boot for 20 seconds. Change-Id: I7461acd7004e3d10cba6665a9bfe25ec8aa6f3ba Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7a075824a1954eb5d1b65ce887304924724a6d21 Original-Change-Id: I7f5968e361333572fd1f84aa11b7150194ad902a Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/261690 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9880 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* storm: add config option to clear dev mode state on recoveryVadim Bendebury2015-04-221-0/+1
| | | | | | | | | | | | | | | | | | | | | Storm and whirlwind devices should leave developer mode as soon as recovery is requested. BRANCH=storm BUG=chrome-os-partner:36059 TEST=with the rest of the patches applies observed desired behavior on SP5 Change-Id: I3e8e481f85cd067eff4fe2049b8aa47e09f6d63e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c6dbafc16edb11ec687359b25098ce8a1b055b91 Original-Change-Id: Iac6fa62229556bc7a6960d7f1630d37570ba72c4 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/261621 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9879 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* google/storm: enable virtual development mode switchVadim Bendebury2015-04-222-1/+2
| | | | | | | | | | | | | | | | | | | | | The whirlwind device is using a button instead of the switch to enable dev mode. BRANCH=storm BUG=chrome-os-partner:36059 TEST=with the rest of the patches applied it is possible to enable and disable dev mode on Whirlwind and the mode persists over reboots. Change-Id: I6d31c8429ea0515bea2b7d707325d9092487048a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 495bd07e3a1d6c587a5f01efa2801d2c4e7edbe8 Original-Change-Id: I8879833ca13074e8275393c3b98df06d56a5361d Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/261416 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9875 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* i2c/ww_ring: use shorter blinking programVadim Bendebury2015-04-221-134/+95
| | | | | | | | | | | | | | | | | | | | | | | | The originally loaded blinking program was written to allow gradual change in LED brightness, which required controlling each LED with its own engine. In fact there is no need in gradual brightness changes when the firmware is controlling the ring. This allows to control all LEDs by one engine, making the code simpler and more robust (no need to synchronize the three engines any more). BRANCH=storm BUG=chrome-os-partner:36059 TEST=verified that recovery boot WW ring patterns work as expected. Change-Id: I89d231fb61693f4e834d8d9323ae5a7ddd149525 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 19809cf8120df8865da9b5b9e7b8e932334bf4b5 Original-Change-Id: I41038fd976dc9600f223dc0e9c9602331baf68f9 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/261026 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9873 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-20 13:23:30 +0000