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* Various CONFIG_DEBUG_RAM_SETUP related fixes (trivial).Uwe Hermann2010-09-257-8/+10
| | | | | | | | | | | | | | Some boards still used the old DEBUG_RAM_SETUP (without _CONFIG prefix). Also, consistently use "#if CONFIG_DEBUG_RAM_SETUP" (not #ifdef) as we do elsewhere. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5843 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Various USB Debug Port fixes (trivial).Uwe Hermann2010-09-258-24/+16
| | | | | | | | | | | | | | | | | | | | | - Drop unused DBGP_DEFAULT #defines on boards with chipsets where no USB Debug Port support is implemented anyway (at the moment, at least): - hp/dl145_g3 - hp/dl165_g6_fam10 - ICH7: Move unrelated code out of set_debug_port(). All ICH southbridges with Debug Port hardcode the physical USB port used as Debug Port to 1. In other words, this port is not user-configurable (as seems to be the case on NVIDIA MCP55). For now we keep the 'port' parameter in order to not change the API, this might be fixed differently later. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5842 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Make globals in romstage break the build, so we don't have to Patrick Georgi2010-09-251-0/+1
| | | | | | | | | | | wonder why variables in .data or .bss (both somewhere in ROM space) are wrong. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5841 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Drop <cpu/amd/mtrr.h> #include from Intel CPUs.Uwe Hermann2010-09-253-3/+0
| | | | | | | | | | | | | | | Three CAR implementations on Intel CPUs include <cpu/amd/mtrr.h>, which is obviously wrong, so drop the #includes. None of their #defines are used in the Intel code. Build-tested with two of the affected boards. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5840 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Keep the mc146818rtc.h include close to the option table include whereMyles Watson2010-09-259-8/+3
| | | | | | | | | | | possible. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5839 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* - Fix race condition in option_table.h generation by moving the includeStefan Reinauer2010-09-2516-21/+47
| | | | | | | | | | | | | | | statement to those files that actually need it. This significantly reduces the number of dependencies, so it's no longer extremely ugly to specify them manually (see the src/pc80/Makefile.inc portion) - Add double include guards around option_table.h defines - Also, drop the AMD DBM690T work around for the issue Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5838 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Make SB600/SB700 more similar for easier diffs (trivial).Uwe Hermann2010-09-2412-68/+53
| | | | | | | | | | | Also fixes random whitespace issues, typos, etc. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5837 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Automatically fetch bus information for mptable fromPatrick Georgi2010-09-249-93/+22
| | | | | | | | | | | | | | | the device tree, instead of using hardcoded values. If this changes behaviour, this is either - a bug in mptable_write_buses(), or - a bug in the old mptable or device config, that is they were inconsistent. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5835 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Undo stupid mistake in r5832Patrick Georgi2010-09-241-1/+0
| | | | | | | | Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5834 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Hook up all AMD SB600/SB700 boards to the EHCI Debug Port infrastructure.Uwe Hermann2010-09-2416-1/+175
| | | | | | | | | | | | | | | Without a (currently) dummy set_debug_port() function the build fails, this may or may not be fixed differently in the future. Manually build-tested on all SB600/SB700 boards, and tested on hardware on one SB600 board I own, works fine. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5833 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix hp/dl165_g6_fam10 build. Failed to take r5800 andPatrick Georgi2010-09-242-0/+3
| | | | | | | | | | | another recent change into account. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5832 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for HP DL165-G6 with Fam10 CPU.Arne Georg Gleditsch2010-09-2414-3/+1214
| | | | | | | | | | | | | Original patch was Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com> Updates to accomodate changes in coreboot are Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5831 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Whitespace/typo/cosmetic fixes (trivial).Uwe Hermann2010-09-237-38/+44
| | | | | | | | | Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5830 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix some wrong capitalizations, reformat comments, fix a typo.Stefan Reinauer2010-09-236-25/+25
| | | | | | | | | Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5829 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* USB Debug Port related license header fixes (trivial).Uwe Hermann2010-09-235-105/+198
| | | | | | | | | | | | | | | | | | | - Add missing license headers, or missing (C) lines to various files. (most are from AMD / Yinghai Lu, based on svn logs) - src/include/ehci.h was taken from the Linux kernel. Updating it to the latest version from git HEAD while I'm at it (build-tested with one board). It also sports some new EHCI 1.1 addendum #defines which we may or may not need. This new file also already has a proper GPL header. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5828 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Generate and extract debug sysmbols for coreboot. *.debug files can beMarc Jones2010-09-233-0/+15
| | | | | | | | | | | used for source level debug. Signed-off-by: Marc Jones <marcj303@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5827 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix a compiler warning in src/lib/usbdebug.c (trivial).Uwe Hermann2010-09-221-6/+6
| | | | | | | | | | | | | | | | | | The 'delay' variable shadows the global 'delay()' function, yielding this compiler warning/error: src/pc80/../lib/usbdebug.c: In function `ehci_reset_port': src/pc80/../lib/usbdebug.c:281: error: declaration of `delay' shadows a global declaration src/lib/delay.c:9: error: shadowed declaration is here This fixes the issue by renaming the 'delay' variable to 'delay_ms'. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5826 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Here is a proposed way how to handle the SATA PHY settings on SB700. It Rudolf Marek2010-09-223-21/+51
| | | | | | | | | | | | | | consits of weak function which always exists (with defaults) and a possibility to override this with normal function in main.c. This is the other way of doing that and not using the devictree.cb. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5825 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* First round of i82801ax clean-ups (trivial).Uwe Hermann2010-09-2111-601/+5
| | | | | | | | | | | | | | | | | | | | | | | | After we splitted up the old i82801xx driver which was supposed to support multiple generations of ICH* chipsets, some of the generified code is now obsolete in i82801ax which should only cover ICH/ICH0 and none of the later ICH* generations. Hence: - Drop "struct pci_driver" entries for chipsets other than ICH/ICH0. - Drop drivers for hardware that is not present on ICH/ICH0: NIC, SATA, EHCI. - Drop PIRQE-PIRQH #defines and code, not available on this chipset. - Simplify some parts of the code (more will follow). Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5824 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Cut the crap.Uwe Hermann2010-09-2173-73/+73
| | | | | | | | | Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5823 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Complete the code which was missing.Zheng Bao2010-09-211-0/+3
| | | | | | | | Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5822 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix the typo. Field DisAutoRefresh is in DramTimngHi.Zheng Bao2010-09-211-1/+1
| | | | | | | | | Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5821 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* A number of cleanups for 440BX raminit code.Keith Hui2010-09-201-30/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | Resolves a number of TODOs items within, and clarified a number of other TODOs. Change register_values[] from long to u8 (byte). For what we are doing this is sufficient and makes it only 1/4 the size. Remove a hard-coding of SDRAMC register that is redundant and now incorrect, now that SDRAMC is conditioned on SDRAMPWR_4DIMM Kconfig and set through register_values[]. This fixes all boards with 3 DIMM slots (e.g. ASUS P2B, A-Trend ATC-6220). RPS registers are now set in runtime code; remove it from register_values[] table. Bring DUMPNORTH() back. The code it refers to is still there. Move #define of NB up so the DUMPNORTH() macro can use it. Signed-off-by: Keith Hui <buurin@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5820 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Make ASUS P3B-F RAM init actually work by enabling SPD access.Uwe Hermann2010-09-194-4/+94
| | | | | | | | | | | | | | | | | | | | | | On this board all reads from SPD return 0xff by default, there's a custom GPIO fiddling needed to enable access to the SPD SMBus offsets at 0x50-0x53. While coreboot actually sort of booted sometimes before r5193, that was just sheer luck as the RAM init was hardcoded in certain ways. Since the proper, more heavily SPD-based RAM init the brokenness of the ASUS P3B-F RAM init was becoming visible. This patch uses GPIOs to enable access to the SPD SMBus offsets, and resets the GPIOs again after RAM init (this is needed to allow for lm-sensors to work, for example). Tested successfully on hardware. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Idwer Vollering <vidwer@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5819 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* AMD Fam10 code breaks with gcc 4.5.0.Scott Duplichan2010-09-172-4/+24
| | | | | | | | | | | | | | | | | | | | Root cause: After function STOP_CAR_AND_CPU disables cache as ram, the cache as ram stack can no longer be used. Called functions must be inlined to avoid stack usage. Also, the compiler must keep local variables register based and not allocated them from the stack. With gcc 4.5.0, some functions declared as inline are not being inlined. This patch forces these functions to always be inlined by adding the qualifier __attribute__((always_inline)) to their declaration. Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5818 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Clear bit 35 of msr c001_102a in Fam10 rev C cores.Arne Georg Gleditsch2010-09-172-2/+4
| | | | | | | | | Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com> Acked-by: Scott Duplichan <scott@notabs.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5817 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add more Fam10 CPUID strings from the AMD revision guide. IncludesMarc Jones2010-09-161-0/+35
| | | | | | | | | | | newer Phenom II. Signed-off-by: Marc Jones <marcj303@gmail.com> Acked-by: Paul Menzel <paulepanter@users.sourceforge.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5815 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* This patch corrects a coding error in the original implementationScott Duplichan2010-09-141-2/+2
| | | | | | | | | | | | | of 'Erratum 343 for AMD Fam10h CPUs' (rev 4345). The original code sets msr c001_102a bit 3 when bit 35 was intended. Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5814 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* IEI Kino added to IEI mainboard Kconfig. I missed this in r5812Marc Jones2010-09-131-0/+3
| | | | | | | Signed-off-by: Marc Jones <marcj303@gmail.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5813 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* IEI Kino mainboard support based on Mahogany Fam10.Marc Jones2010-09-1323-0/+5366
| | | | | | | | | | | svn copy amd/mahogany iei/kino-780am2-fam10; then apply the patch. Signed-off-by: Marc Jones <marcj303@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5812 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* CONFIG_MMCONF_SUPPORT is always defined. Fix build.Myles Watson2010-09-131-1/+1
| | | | | | | | Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5811 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Move initialization of MMCONF BAR to cache_as_ram setup phase, in orderArne Georg Gleditsch2010-09-133-35/+16
| | | | | | | | | | | | | | | to make sure MMCONF is set up before use. Otherwise, PCI config accesses run before init_cpus() will be lost if MMCONF is enabled (unless explicitly done as port-based accesses). This obsoletes removal of RES_PCI_IO, PCI_ADDR(0, 1, 0, 0x78) in mcp55_early_setup, so reinsert. Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5810 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for Asus M4A785-M.Juhana Helovuo2010-09-1324-0/+5470
| | | | | | | | Signed-off-by: Juhana Helovuo <juhe@iki.fi> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5809 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add reserved areas for fam10.Myles Watson2010-09-131-1/+18
| | | | | | | | Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5808 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Port k8 UMA handling to fam10.Myles Watson2010-09-131-0/+11
| | | | | | | | Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5807 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Generate multiboot tables from coreboot tables.Juhana Helovuo2010-09-133-80/+42
| | | | | | | | Signed-off-by: Juhana Helovuo <juhe@iki.fi> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5806 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Print an error and correct pci scan limits. Skip sb700 ISA DMA init if needed.Juhana Helovuo2010-09-133-0/+18
| | | | | | | | Signed-off-by: Juhana Helovuo <juhe@iki.fi> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5805 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Fix a typo reported by Sylvain Hitier.Myles Watson2010-09-131-1/+1
| | | | | | | | Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5804 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Convert i945 boards to use reserved resources instead of directly addingMyles Watson2010-09-1310-40/+17
| | | | | | | | | | coreboot table entries in every mainboard. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5803 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add F71859 SIO.Marc Jones2010-09-107-0/+224
| | | | | | | | | Signed-off-by: Marc Jones <marcj303@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5802 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for LiPPERT Hurricane-LX (EPIC board with AMD Geode-LX,Jens Rottmann2010-09-107-0/+501
| | | | | | | | | | | | | | CS5536, ITE IT8712F). Board support is based on the SpaceRunner-LX (with tiny bits from the RoadRunner-LX) even though the hardware really was the ancestor of our three other -LX boards and in fact among the earliest Geode-LX boards on the market. (Might even have been the first Geode-LX EPIC?) Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5801 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Move memory type information out of some AMD sockets.Myles Watson2010-09-1032-36/+114
| | | | | | | | Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5800 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Adapt comment, too. (trivial)Patrick Georgi2010-09-091-1/+1
| | | | | | | | | Noticed-by: Uwe Hermann Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5799 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* This patch avoids a timeout during PS/2 keyboardScott Duplichan2010-09-091-1/+1
| | | | | | | | | | | initialization. It can reduce KBC init time by up to 400 ms on real hardware, and by a minute or so on AMD simnow. Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5798 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Make huge macros inline functions for readability. Remove warnings. Trivial.Myles Watson2010-09-092-165/+165
| | | | | | | | Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5797 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Please find appended. This patch gets rid of the %gs magic altogether,Arne Georg Gleditsch2010-09-0910-40/+73
| | | | | | | | | | | | | fixes a few alignment wrinkles and sets up and registers the MMCONF area for AMD Fam10h CPUs (where selected by mainboard configuration). It removes a bit of code that proved troublesome in MMCONF setups from mcp55_early_setup_car.c, as per earlier discussion. Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5796 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add support for reserved regions to resources and coreboot tables.Myles Watson2010-09-092-0/+18
| | | | | | | | Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5795 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* My Jmicron SATA card writes the name of the hard drive to the screen.Myles Watson2010-09-091-2/+77
| | | | | | | | | | | This redirects that output to the console and implements a basic keyboard stub. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5793 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Also improve boot time on AMD for the DDR3 code path.Arne Georg Gleditsch2010-09-092-2/+2
| | | | | | | | | | Fix a typo, too. Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numscale.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5792 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Apparently, it's not crucial to clear this at the exact moment we switchArne Georg Gleditsch2010-09-092-1/+6
| | | | | | | | | | | to using ram, so something like the appended is perhaps more appropriate. Confirmed to work on hw. Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numscale.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5791 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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