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* mb/facebook/monolith: Make use of the chipset devicetreeFelix Singer2023-11-131-22/+19
| | | | | | | | | | | Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: Ib1adeaf4745804dfc91f99fb4e4491b68631202c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
* mb/lenovo/x220: Update devicetreePatrick Rudolph2023-11-131-4/+7
| | | | | | | | | | | | | | | | | - Disable unconnected PCH PCIe ports 1 + 3. - Add smbios_slot_desc to WLAN PCIe port - Add comment for PCIe port 7 that might have a XHCI controller connected (some variants only). Test: Lenovo X220 still boots and all devices are still working fine. The WLAN slot is shown in dmidecode -t 9. Change-Id: I3fdfbb7ad30e2ff8a289d9055eaef0557475fdff Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* mb/libretrend/lt1000: Make use of the chipset devicetreeFelix Singer2023-11-131-34/+19
| | | | | | | | | | | Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: I6ba850c783999d06c73137ed77d32fc108a20347 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79034 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
* mb/starlabs/starbook/kbl: Use chipset dt reference name for LPCFelix Singer2023-11-131-1/+1
| | | | | | | | Change-Id: I41b3ed4926fe77c5729672fd7a7bcb8ca0c5c216 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79033 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/hp/280_g2: Make use of the chipset devicetreeFelix Singer2023-11-131-46/+22
| | | | | | | | | | | Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: Ib6edae61fb904143c3b3994df812524a258fa9f3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/asrock/h110m: Make use of the chipset devicetreeFelix Singer2023-11-131-48/+17
| | | | | | | | | | | Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: I9f92246da4a500e85c878d865d621033f6b35f1b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
* nb/intel/sandybridge: Clean up post Haswell SPD mapping API migrationKeith Hui2023-11-133-27/+2
| | | | | | | | | | | | | | | | | | | | | With migration to Haswell SPD mapping interface complete: 1. Remove weak stubs meant to ensure smooth transition and internalizes mainboard_get_spd() within raminit.c. 2. Remove post-mainboard SPD data sanitization code in raminit_mrc.c, now that it fills its own SPD data. 3. Remove old prototypes from raminit_native.h 4a. Drops raminit_native.h from raminit.c, as individual headers therein are already included. 4b. Drop another header from raminit.c IWYU identified as unneeded. asus/p8z77-m still builds afterwards. (sandybridge to receive a full IWYU cleanup later.) Change-Id: Ie073c1386cd0a645069f0e1416263b4fa359b74b Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76991 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/*: Update SPD mapping for sandybridge boardsKeith Hui2023-11-13112-672/+104
| | | | | | | | | | | | Boards without HAVE_SPD_IN_CBFS: Move SPD mapping into devicetree. Boards with HAVE_SPD_IN_CBFS: Convert to Haswell-style SPD mapping. Change-Id: Id6ac0a36b2fc0b9686f6e875dd020ae8dba72a72 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* mb/apple/macbookair4_2: Correctly implement SPD mapping the Haswell wayKeith Hui2023-11-134-15/+39
| | | | | | | | | | | | | | | | | | | | | | | While converting this board to provide SPD info using the Haswell API, it was discovered that its SPD setup was not correct to begin with. For a board that only has soldered down memory with SPD data in CBFS, it didn't enable HAVE_SPD_IN_CBFS in Kconfig. It also duplicated one set of SPD data with deliberate gaps in between. It worked its dark magic within mainboard_get_spd(), which is going away as a callback. Add HAVE_SPD_IN_CBFS to mainboard Kconfig, recreate the one set of SPD data as a hex dump same as other boards, and hook everything back up with Haswell-style mb_get_spd_map(). Recreated SPD data was extracted from abuild-built binary and manually verified for correctness against existing spd.bin (which will be removed in a follow-up). Change-Id: I906c49f6d1949f830828530edc0298b1b22ec04d Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76995 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/sandybridge: Standardize MRC vs. native SPD mapping APIKeith Hui2023-11-134-11/+137
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changes both MRC and native raminit code path to get SPD mapping from one place. Boards with all memory socketed specify their mappings in a devicetree setting introduced in commit 5709e03613b3 ("nb/intel/sandybridge: Migrate MRC settings to devicetree") back in May 2019 but remains unused as of this patch. This setting will now hold raw SMBus addresses, and MRC raminit gets code to translate them into a representation MRC expects. Boards with soldered down memory (specifically with HAVE_SPD_IN_CBFS in their board Kconfig), with or without socketed memory, specify their layouts in mb_get_spd_map() as used by Haswell boards, where they access hardware GPIO straps to select which SPD data to use. This harmonizes the way boards specify their SPD layouts across Haswell/SNB/IVB boards whether using MRC or native raminit. Going forward they only need to specify the layout in one place. (Going forward the devicetree setting should be backported to Haswell, once we get native raminit working there.) With this, northbridge code is now fully responsible for loading all SPD data, be it from CBFS or SMBus. To avoid breakage, transition will happen in stages: 1. This patch gets all the code in, and implements weak stubs that maintain existing code and data flow (i.e. mainboards still populate final SPD layout data). At this point devicetree already uses new representation, but is still unused meaning no breakage. 2. Follow-up patch(es) remove mainboard_get_spd() from mainboards, and replace it with mb_get_spd_map() or devicetree values (as appropriate) with converted SPD info. The "weak" mainboard_get_spd() with new logic takes over. Boards go Haswell Style at this point. Boards with MRC raminit also lose code to fill in SPD data, allowing new data to take hold. 3. Clean-up patch removes the weak functions and public prototypes re mainboard_get_spd(), making it internal to northbridge. Changeover is complete. Change-Id: I1a75279d981e46505930a9ce1aae894ccc4e1f24 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76965 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/51nb/x210: Make use of the chipset devicetreeFelix Singer2023-11-131-34/+14
| | | | | | | | | | | Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: I0f069f02e4f0957cbff05d1bc9aa499fb51b6a02 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78574 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* soc/amd/genoa: Hook up MCA codeArthur Heymans2023-11-134-0/+63
| | | | | | | | | | | | This patch uses AMD SoC common code for MCA and adds MCA bank information as per Genoa Processor Programming Reference (PPR) version 0.25 (#55901) and uses AMD SoC common code. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: If728d803d600f7e86507cd1b35b40022bf4d379e Reviewed-on: https://review.coreboot.org/c/coreboot/+/76524 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/genoa: Hook SMP and SMM initArthur Heymans2023-11-136-2/+142
| | | | | | | | | | All CPUs properly come out of reset and relocate SMM. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I8c2d976addacd5a2ba70eb629510128853b9f847 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/genoa: Double HEAP_SIZE to 0x200000Varshit Pandya2023-11-131-0/+5
| | | | | | | | | | | Default value of HEAP_SIZE is 0x100000, since genoa has a lot of CPU increase the HEAP_SIZE to 0x200000 Change-Id: Idd707200fe72730849267cd3cafc40e44f1f8c5d Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* security/vboot: Die if vb2api_reinit() failedYu-Ping Wu2023-11-131-3/+7
| | | | | | | | | | | | | | | | | | | | | | | In vboot_get_context(), vb2api_reinit() is called to restore the vboot context from the previous stage. We use assert() for the return value of vb2api_reinit() because there shouldn't be runtime errors, except for one edge case: vb2_shared_data struct version mismatch. More precisely, when RW firmware's VB2_SHARED_DATA_VERSION_MINOR is greater than RO's, vb2api_reinit() will return VB2_ERROR_SHARED_DATA_VERSION. To avoid using an invalid vb2_context pointer (when FATAL_ASSERTS is disabled), change assert() to die() on vb2api_reinit() failure. For the vb2api_init() case the assertion is unchanged because there shouldn't be any runtime error for that. Also move the vb2api_init() call outside the assert() argument, as assert() may be a no-op macro depending on the implementation. Change-Id: I4ff5ef1202bba2384c71634ec5ba12db1b784607 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* mb/google: Remove obsolete Kconfig symbol VBT_DATA_SIZE_KBMartin Roth2023-11-132-8/+0
| | | | | | | | | | | | | | | The symbol VBT_DATA_SIZE_KB was removed in commit 8bde652241 - "drivers/intel/gma/opregion: Use CBFS cache to load VBT" CB:77886, however that patch only removed the Kconfig option from the Intel chipsets, leaving it unused in the mainboards. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ia29d8d6ec17b172e662ff591849f1668d65f1ff9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78967 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Eric Lai <ericllai@google.com>
* fmap: Map less space in fallback path without CBFS verificationJulius Werner2023-11-132-1/+5
| | | | | | | | | | | | | | This is a fixup to CB:78914 which inadvertently broke the RK3288 SoC. Unfortunately we can only accommodate very little PRERAM_CBFS_CACHE in the tiny SRAM for that chip, so we would not be able to map an entire FMAP. Solve this problem for now by mapping less space when CBFS verification is disabled, and disallowing CBFS verification on that SoC. Change-Id: I2e419d157dc26bb70a6dd62e44dc6607e51cf791 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78971 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* drivers/pc80/rtc/option.c: Reset only CMOS range covered by checksumBill XIE2023-11-131-2/+5
| | | | | | | | | | | | | | | | | | | | | | | Proposed in the comment of commit 29030d0f3dad ("drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume"), during sanitize_cmos(), only reset CMOS range covered by checksum and the checksum itself from the file cmos.default in CBFS, in order to prevent other runtime data in CMOS (e.g. the DRAM training data on GM45 platforms for s3 resume) being erased. Tested: cherry-pick this commit before commit 44a48ce7a46c ("Kconfig: Bring HEAP_SIZE to a common, large value"), which is already before my commit 29030d0f3dad , Thinkpad X200 with CONFIG(STATIC_OPTION_TABLE) can resume from s3 again, indicating that DRAM training data are no longer erased. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Co-authored-by: Jonathon Hall <jonathon.hall@puri.sm> Change-Id: I872bf5f41422bc3424cd8631e932aaae2ae82f7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/78906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
* security/tpm/: turn tis_{init,open} into tis_probeSergii Dmytruk2023-11-1311-159/+121
| | | | | | | | | | | | | | | | | init() was always followed by open() and after successful initialization we only need send-receive function which is now returned by tis_probe() on success, thus further reducing number of functions to export from drivers. This also removes check for opening TIS twice that seems to have no value. Change-Id: I52ad8d69d50d449f031c36b15bf70ef07986946c Ticket: https://ticket.coreboot.org/issues/433 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76954 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arch/x86/riscv: Use 'all' target to include files in all stagesArthur Heymans2023-11-131-50/+22
| | | | | | | | | | | | This adds a few new files to romstage, that will be needed in follow-up patches. Change-Id: I2ba84e0becee883b5becf12e51f40734cad83d7d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68839 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
* Update genoa_poc/opensil submodule to upstream mainMartin Roth2023-11-131-0/+0
| | | | | | | | | | | | | | | | | Updating from commit id d81517e: 2023-09-28 14:13:56 -0600 - (Improper bit field offset calculation) to commit id 0411c75: 2023-11-10 23:59:34 +0000 - (Minor changes to fix issues compiling with clang) This brings in 1 new commits: 0411c75 Minor changes to fix issues compiling with clang Change-Id: Ib3adfd7bccd45dfd76ede462677dcfb294baa15d Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* acpi/acpigen: point out what acpigen_write_len_f doesFelix Held2023-11-131-0/+2
| | | | | | | | | Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibaf2f54f2f428f4438ef22b7f9d205db10e144db Reviewed-on: https://review.coreboot.org/c/coreboot/+/79001 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* arch/riscv/ramstage.S: Add comments for passed argumentsMaximilian Brune2023-11-131-1/+6
| | | | | | | | Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Ib1af1359249008d9eba351271637748a7edcec26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78966 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/nissa/var/gothrax: Add GPIO configurationYunlong Jia2023-11-133-0/+87
| | | | | | | | | | | | | | | | | | | | | Add variant of LTE and WFC support on gothrax board. We base decisions on the values within the firmware configuration CBI field. In fw_config settings, if the board move LTE and WFC modules, the hardware GPP_A8/GPP_E13/GPP_F12/GPP_H19/GPP_H23/GPP_R6/GPP_R7 pins need to be deasserted. BUG=b:303526071 TEST=emerge-nissa coreboot & \ Check against schematic. Whether it works as expected under different SKUs. Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: Ia8041bdc599509911bde95d6294314036e75b227 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78916 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
* mainboards: Drop stale comment about enumerate_buses()Nico Huber2023-11-1231-99/+0
| | | | | | | | | | | | | There is no enumerate_buses() today and also no trace of it in our repository. Also, in current terms, mainboard_enable() is called as the very first thing in our enumeration so the comment seems misleading. Change-Id: Iae620f83c8166c1cfc8b9fb9ef4a7025987bf1be Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* rockchip/rk3288: Reshuffle memlayout to make a bit more verstage spaceJulius Werner2023-11-111-6/+6
| | | | | | | | | | | | | RK3288 is bursting at the seams again. This patch reshuffles two more kilobytes to verstage to make things fit a little better. Change-Id: I5e7667061dce3d02441be83c0b8fb81500a1b1a3 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78970 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* acpi/acpigen: Fix buffer length in acpigen_write_name_unicode()Matt DeVillier2023-11-111-1/+1
| | | | | | | | | | | | | | | | | The buffer length is in bytes, and since we are converting from ASCII to UTF-16, the value written needs to be 2x the string length + null terminator. TEST=build/boot google skyrim (frostflow), dump acpi and check bytecode for correct buffer length preceding unicode strings. Change-Id: Id322e3ff457ca1c92c55125224ca6cfab8762a84 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78977 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/clevo/kbl-u: Move selects from Kconfig.name to KconfigFelix Singer2023-11-112-1/+3
| | | | | | | | | | | | Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I51b3bca2421b64f73d4d3c0d9346a1416bf15f35 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78976 Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/amd/birman: Use common option for variant configurationFelix Singer2023-11-111-10/+12
| | | | | | | | | | | | | | | | | | When a variant setup is used, checking for each variant in order to do the mainboard configuration is quite painful. Thus, move the selects from BOARD_SPECIFIC_OPTIONS, which is enabled by default when a variant is chosen, out to a common option, which is disabled by default but selected by the variants. So in order to enter that config block, it's only needed to check if that common option is enabled and not for each variant. It's also a very common scheme now. Change-Id: I4ed889ce78a0d7cd088e05d0f4b7fbbc89153860 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* mb/amd/birman: Move selects from Kconfig.name to KconfigFelix Singer2023-11-112-2/+6
| | | | | | | | | | | Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I836c35e6bbfa77d536065a4237ef85a170df9fdb Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* mainboard/msi/ms7e06: Remove FSP_TYPE_IOTMichał Żygowski2023-11-101-1/+0
| | | | | | | | | | | | | | | MSI PRO Z790-P is not an IoT platform. FSP_TYPE_IOT was selected only temporarily to allow builds from public components. Now that Client FSP is available, switch to it. TEST=Build and boot MSI PRO Z790-P Change-Id: Ic5d84e48d58c3454b83b9df5eb93076d2ebde000 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
* soc/intel/alderlake: Allow using FSP repo for all RPL-S platformsMichał Żygowski2023-11-101-1/+1
| | | | | | | | | | | | | | | The Client FSP for Raptor Lake-S is present on the Intel FSP repository, so there is no need to restrict Raptor Lake-S FSP binary repository to IoT only. TEST=Build and boot MSI PRO Z790-P Change-Id: I77aecd6e2d753732bf6358afe2c7ea0491348387 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-by: Eric Lai <ericllai@google.com>
* soc/alderlake: Fix order of defaults in FSP_HEADER_PATHMichał Żygowski2023-11-101-1/+1
| | | | | | | | | | | | | | | | | | | | The combination of SOC_INTEL_RAPTORLAKE_PCH_S and FSP_TYPE_IOT is currently broken. By default, e.g. for MSI PRO Z790-P, the FSP_HEADER_PATH does not match the default FSP_FD_PATH. For headers the client FSP is selected, while for the FD file, IoT FSP binary is chosen. The order of default for both headers and FD file must be the same to match the headers and binaries. TEST=Build default MSI PRO Z790-P config and see that FSP_HEADER_PATH matches FSP_FD_PATH FSP variant-wise. Change-Id: I8db5ea10c2986ff8d3fa7d616b3f1617d05f0260 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78410 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/meteorlake: Set DTT PCI device IRQ to INT_A/PIRQ_AJeremy Compostella2023-11-101-1/+3
| | | | | | | | | | | | | | | | | The Dynamic Tuning Technology (DTT) device IRQ is not programmable and is INT_A/PIRQ_A (IRQ 16). Reference: Meteor Lake U/H and U Type4 External Design Specification External Design Document (657165) TEST=Linux driver successfully uses IRQ 16 on rex. Without this patch it was binding IRQ 18 but interrupts were going to IRQ 16. Change-Id: I2cbb9dd41f27c40a29346be325bb9c46d1061afb Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/siemens/{mc_ehl3,mc_ehl5}: Fix GPIO settings for latest HW revisionMario Scheithauer2023-11-102-2/+2
| | | | | | | | | | | | | | With the latest hardware revision of both mainboards, native function two of GPIO B23 (PCHHOT_N) is used for diagnostic purposes. BUG=none TEST=Checked output verbose GPIO debug messages Change-Id: Ibe130b5d4c74576294183221765c5f4db9b5ec2a Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78962 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device/Kconfig: rename AZALIA_PLUGIN_SUPPORT to AZALIA_HDA_CODEC_SUPPORTFelix Held2023-11-1014-16/+21
| | | | | | | | | | | | Rename AZALIA_PLUGIN_SUPPORT to AZALIA_HDA_CODEC_SUPPORT and add a help text to this Kconfig option to clarify what this option is about. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I71e36869c6ebf77f43ca78f5e451aebfb59f1c74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* src: Remove unnecessary semicolons from the end of macrosMartin Roth2023-11-102-2/+2
| | | | | | | | | Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ia005915a05d02725f77b52ccd7acebefaf25d058 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78964 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cpu/x86/smm: Fix get_save_state calculationEugene D. Myers2023-11-103-5/+13
| | | | | | | | | | | | | | | | | | | | When the SMI transfer monitor (STM) is configured, get_save_state returns an incorrect pointer to the cpu save state because the size (rounded up to 0x100) of the processor System Management Mode (SMM) descriptor needs to be subtracted out in this case. This patch addresses the issue identified in CB:76601, which means that SMMSTOREv2 now works with the STM. Thanks to Jeremy Compostella for suggesting this version of the patch. Resolves: https://ticket.coreboot.org/issues/511 Change-Id: I0233c6d13bdffb3853845ac6ef25c066deaab747 Signed-off-by: Eugene D. Myers <edmyers@cyberpackventures.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/google/rex/var/screebo: Update DFP portzhourui2023-11-101-4/+4
| | | | | | | | | | | | | | | Update DFP port setting for retimer power GPIO BUG=b:302428013 BRANCH=none TEST=Retimer enumaration in NDA works. Change-Id: Idc1a728ec4cbb66e776c2700025db41d85801c60 Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya/Kconfig.name: Remove duplicate selectFelix Singer2023-11-101-1/+0
| | | | | | | | | | | | | That select is duplicate to the ones in the Kconfig file, and it shouldn't be there anyway. Remove it. Change-Id: I1a940f034a69f72280d15ab9a0c9d83f8111910e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78973 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brox: Remove use of EC_IN_RW_OD GPIOShelley Chen2023-11-092-9/+1
| | | | | | | | | | | | | | | Later GSCs don't need a EC_IN_RW GPIO anymore, so removing the use of this for get_ec_is_trusted(). BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I29f94969e9f2c1f239d9f9655f39b8410296f695 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* Allow to build romstage sources inside the bootblockArthur Heymans2023-11-0944-65/+113
| | | | | | | | | | | | | | | | | | | | | | | Having a separate romstage is only desirable: - with advanced setups like vboot or normal/fallback - boot medium is slow at startup (some ARM SOCs) - bootblock is limited in size (Intel APL 32K) When this is not the case there is no need for the extra complexity that romstage brings. Including the romstage sources inside the bootblock substantially reduces the total code footprint. Often the resulting code is 10-20k smaller. This is controlled via a Kconfig option. TESTED: works on qemu x86, arm and aarch64 with and without VBOOT. Change-Id: Id68390edc1ba228b121cca89b80c64a92553e284 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55068 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd: Remove unnecessary choice symbol name from PSP KconfigMartin Roth2023-11-091-1/+1
| | | | | | | | | | | | | | There's no reason to name this choice block. Remove the name. Change-Id: Iebf8b1e7af928b988ab514d9dd85d2e70bf00c09 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78917 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/nissa/var/gothrax: Add FW_CONFIG probe about DB/WFCYunlong Jia2023-11-091-7/+24
| | | | | | | | | | | | | | | | Add FW_CONFIG probe to separate WFC settings. WFC_PRESENT/WFC_ABSENT Add FW_CONFIG probe for new DB_USB sku. DB_C_A_LTE/DB_A BUG=b:303526071 TEST=emerge-nissa coreboot Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I93e0bce4b8be37e259efe0d7b0185035b3e88785 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78963 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/rex/variants/deku: Add display configurationEran Mitrani2023-11-091-0/+8
| | | | | | | | | | | | | Enable DDI on ports 1 to 4 for Type-C DisplayPort. BUG=b:305793886 TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I3acaff4a9306f2d058ce9542e8956ee0acba94cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/78498 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/rex: split TOUCHSCREEN_I2C_SPI definitionYH Lin2023-11-081-7/+8
| | | | | | | | | | | | | | | As TOUCHSCREEN_I2C_SPI will be used for two different configurations, splitting it to TOUCHSCREEN_GSPI and TOUCHSCREEN_THC, and re-order the FW_CONFIG bits by moving VPU to different bit position. BUG=b:307774932 TEST=build and boot rex Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: Ied4d732ef7993e95edbb7eb281842b9392e72820 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brox: Configure early GPIOs in bootblockShelley Chen2023-11-081-0/+8
| | | | | | | | | | | | | | | | Some GPIOs (like WP and GSC) need to be configured in bootblock. Making sure that they get configured earlier for this. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I8dd4853bc05b954f47d858d87ea2aed48e4b8074 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78943 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brox: Correcting GPIOs based on latest schematicsShelley Chen2023-11-081-131/+140
| | | | | | | | | | | | | | | | | There are some inaccuracies in arbitrage. This is the first pass at correcting the incorrectly generated configs. I also tried to update the "No heuristic was found useful" comment generated by arbitrage into something more useful (ie: the appropriate NFs). BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I836565e09a3e0b25746b3e2f9ed6610eaacf7e97 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78942 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/anraggar: Initialise overridetreewuweimin2023-11-083-2/+458
| | | | | | | | | | | | | | | Initialise overridetree based on the schematics revision 20231020A. Added data.vbt just only for running abuild completed. Real vbt define by CONFIG_INTEL_GMA_VBT_FILE in chromium:4936896. BUG=b:304920262 TEST=abuild -v -a -x -c max -p none -t google/brya -b anraggar Change-Id: I232bde990747be80e1ab62c3f0d010d5fc854cb5 Signed-off-by: wuweimin <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78456 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/anraggar: Add initial GPIOs configwuweimin2023-11-083-0/+128
| | | | | | | | | | | | | Configure GPIOs according to schematics revision 20231025G. BUG=b:304920262 TEST=abuild -v -a -x -c max -p none -t google/brya -b anraggar Change-Id: I7be6829fc27ee20e014c372d704333ebfd4967b8 Signed-off-by: wuweimin <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-03 19:17:57 +0000