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* nb/intel/sandybridge: Fix unitialized variable issue4.22.014.22_branchJeremy Compostella2023-11-231-1/+1
| | | | | | | | | | | | | | | | | | | | | Cherry-picked from main branch using commit caa0c0e71a. Original commit message: commit 1e9601c5ef80 ("nb/intel/sandybridge: Standardize MRC vs. native SPD mapping API") introduced an uninitialized variable issue. Change-Id: I41b081dc4c961acc04423067e29e0eabe5f17539 Found-by: Coverity CID 1524317 Original-Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/79093 Original-Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* mb/google/brox: Use Ti50 configShelley Chen2023-11-182-1/+2
| | | | | | | | | | | | | | Brox is using Ti50, so make sure that we set the right config for that. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: If4a16448eebc028b2989c1de150b9e0f9067ee92 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brox: Fix GPIO assignments in gpio.hShelley Chen2023-11-182-8/+8
| | | | | | | | | | | | | | | | | Assigning the macros in gpio.h to the correct GPIOs. Also, fixing GPE configurations so that they are mapped to the proper wake sources (GPP_B, D, E groups). BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I6320cd98e560e514e63c52e173cb7923cfd1cdee Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* qualcomm/sc7180: Move QCSDI and increase romstage size by 4KBJulius Werner2023-11-181-2/+2
| | | | | | | | | | | | | | | | | | We need to increase romstage size a little to make a compiler upgrade fit (CB:70771). Unfortunately the end of the romstage directly touches the QCSDI region in the current memlayout, and there is no other way to reshuffle things to make more space... so we need to move QCSDI out of the way. This means that anyone who is actually building this platform with CONFIG_QC_SDI_ENABLE (which requires a proprietary blob that's not publicly available) will need to recompile their QCSDI binary to match the new start address. Change-Id: Iaf13e4001b3c763e3ec59009779931ec75603d5d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79074 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* mb/google/herobrine: Move selects from Kconfig.name to KconfigFelix Singer2023-11-172-9/+27
| | | | | | | | | | | Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I25b7adccf60abe515d129f8d00383165eccf6431 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79028 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/trogdor: Move selects from Kconfig.name to KconfigFelix Singer2023-11-172-13/+39
| | | | | | | | | | | Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I30a15277527a1e423691ff55ff11cc2136cefc90 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* soc/qualcomm/{sc7180,sc7280}: Allow building without QC blobs repoFelix Singer2023-11-175-17/+9
| | | | | | | | | | | | | | | | | | Building coreboot for the Qualcomm SoCs SC7180 and SC7280 requires to include the Qualcomm blobs, which requires to accept their license. However, for various reasons it makes sense to build without blobs, e.g. static analysis or just build-testing. So in order to do that, run the steps integrating the Qualcomm blobs into the coreboot binary only if USE_QC_BLOBS is enabled and also remove guards which prevent building related mainboards when USE_QC_BLOBS is not enabled. Change-Id: I249ac477b8f10e7fa0848e967c23a3b3b9bbd27d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79026 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/amd/pi/00730F01: add CPU and domain ops in devicetreeFelix Held2023-11-172-14/+6
| | | | | | | | | | | | | | Add the CPU and PCI domain operation bindings statically in the chipset devicetree instead of adding them during runtime. TEST=PC Engines APU2 still boots and doesn't show any new problems Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I44fa57458c408e74a6341643620c5e9ac1817557 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* nb/amd/pi/00730F01: restructure chip opsFelix Held2023-11-176-57/+42
| | | | | | | | | | | | | | | | Since this chip is a SoC and also to bring the chipset devicetree more in line with the chipset devicetree of Sandy Bridge, merge the chip operations of the northbridge's root complex and the northbridge itself into one chip operations structure and use it at the top level of the devicetree. TEST=PC Engines APU2 still boots and doesn't show any new problems Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8b42bac07b1409bbc797bc4428cf9f84a40e94c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* nb/amd/pi/00730F01: introduce and use chipset devicetreeFelix Held2023-11-176-148/+118
| | | | | | | | | | | | | | | BKDG #52740 Rev 3.05 was used as a reference for the SoC's various PCI devices. The HDA controller in the FCH at function 2 of device 0x14 on bus 0 was missing in the mainboard's devicetrees. TEST=PC Engines APU2 still boots and doesn't show any new problems Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6970c2f6e6d661d40406586f4e6eeb05bcd07979 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79083 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* include/device/device: drop HAVE_ACPI_TABLES guardsFelix Held2023-11-171-2/+1
| | | | | | | | | | | There's no need to remove the corresponding fields from the device_operations struct when HAVE_ACPI_TABLES isn't selected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iac20b6cdc44a5280566ee7003a5ef6fbe913b099 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78990 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* include/device/device: drop GENERATE_SMBIOS_TABLES guardsFelix Held2023-11-171-2/+2
| | | | | | | | | | | There's no need to remove the corresponding fields from the device_operations struct when GENERATE_SMBIOS_TABLES isn't selected. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifa24d1fd211c263b788046e63de3dd5c54cba801 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/google/corsola: Configure I2C and I2S interface for ALC5650wuyang52023-11-171-2/+20
| | | | | | | | | | | | | | | | | Configure I2S1 and I2C5 for ALC5650 to support beep sound in depthcharge. BRANCH=corsola BUG=b:305828247 TEST=Verify devbeep in depthcharge console Change-Id: Ibd098adb8d5568ad338bbfece0edfd0c38cbf854 Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79064 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/zork/morphius: Drop touchscreen detectionMatt DeVillier2023-11-171-1/+0
| | | | | | | | | | | | | | | | Morphius boards using pre-v3.6 schematics don't have a dedicated GPIO for touchscreen power/enable, and so fail with runtime detection enabled. Since it only has one touchscreen option, and no SKUs lack a touchscreen, we can safely assume it is present in all cases. TEST=build/boot morphius w/4k screen, verify touchscreen enabled in cbmem and functional in Linux and Windows. Change-Id: I13e07e14b5a18fa1dd3b18950cf46e9d7821eedc Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* ec/google/chromeec: Update ec_cmd_api.h and ec_commands.hSimon Glass2023-11-162-6/+471
| | | | | | | | | | | | | | | | | | | Generated using update_ec_headers.sh [EC-DIR]. The original include/ec_commands.h version in the EC repo is: ab9b64ac4c Add a host command to print info about AP-firmware state The original include/ec_cmd_api.h version in the EC repo is: ab9b64ac4c Add a host command to print info about AP-firmware state BUG=b:300525571 BRANCH=none TEST=none Change-Id: I3570e073a91621cb1d28a24aa35c1f4beedceaab Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79066 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* acpi/device: Only return dev->ops->acpi_name if non-NULLCoolStar2023-11-161-2/+5
| | | | | | | | | | | | | | | | | | Returning a NULL device name can cause issues if something else does handle it. E.g. UART and GNA devices on Intel Alder Lake-N cause INTERNAL_POWER_ERROR BSOD's in Windows when enabled due to invalid packages being created from a NULL name Test: build/boot google/nissa (craaskvin) to Win11 Change-Id: I0679147ad3e330d706bbf97c30bc11b2432e2e8a Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/google/skyrim/frostflow: Drop GPIO override for camera shutterMatt DeVillier2023-11-161-2/+0
| | | | | | | | | | | | | | | | | Appears to not be used under Windows, Linux, or ChromeOS, and causes high CPU usage at idle under Windows. BUG=none TEST=build/boot Win11, Linux on google/frostflow, verify camera shutter function unchanged, CPU usage under Windows idles where expected. Change-Id: I8a6ea3b886766bdb055b40949c75bec0264eecc5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/system76/rpl: Allow 5600 MT/s memory for RPL-HXMatt Parnell2023-11-163-6/+6
| | | | | | | | | | | | | | | | | | System76 only sells units with memory speeds up to 5200 MT/s, but the i9-13900HX supports up to 5600 MT/s memory. Tested by running memtest and checking dmidecode reports 5600 MT/s when using 2x16 GB 5600 MT/s Crucial SODIMMs (CT2K16G56C46S5) on addw3, bonw15, serw13. Change-Id: I9bb0435769c70c1db06d2c5cca2dd28eb5331f49 Signed-off-by: Matt Parnell <mparnell@gmail.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Tested-by: Levi Portenier <levi@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78912 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/supermicro/x11: Make use of chipset devicetreeFelix Singer2023-11-165-92/+54
| | | | | | | | | | | Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: I5176aa56ecaa52d0f42455bc7176b0415a6199ec Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78594 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/geralt: Disable SD card support for CiriRuihai Zhou2023-11-161-1/+2
| | | | | | | | | | | | | | | According to proto schematics, the SD card is removed. BUG=b:308968270 TEST=emerge-geralt coreboot BRANCH=None Change-Id: Id4e021e7896d093560f39c40573ac616d76438c2 Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
* mb/google/geralt: Move backlight-related functions to common panel.cRuihai Zhou2023-11-164-38/+45
| | | | | | | | | | | | | | | | | These backlight related functions can be reused in other variants, move them out to the panel.c. Also the panel_geralt.c should be used for Geralt, enable it on Geralt board only. BUG=b:308968270 TEST=emerge-geralt coreboot BRANCH=None Change-Id: I5d4035d5f480551c428c450826e23bf77f2fe08a Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78955 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
* lib/device_tree.c: Fix print_propertyMaximilian Brune2023-11-161-3/+7
| | | | | | | | | | | | | | | | | | | | | This uses the size attribute to traverse the possible string. This patch traverses the entire property for non printable characters and not just until the first 0 is hit. Now numbers that start with a zero (memory wise) are not falsely recognized as strings: before the patch: clock-frequency = ""; after the patch: clock-frequency = < 0x1c2000 >; Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I229c07b76468fe54f90fa9df12f103d7c7c2859d Reviewed-on: https://review.coreboot.org/c/coreboot/+/78025 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* drivers: spi_flash: Add space before colon to fix coding styleTyler Wang2023-11-161-2/+2
| | | | | | | | | | | | BUG=none TEST=build karis firmware pass Change-Id: I67b4ca4c8fde795d4206eaa0b9ea9d9bfc768ac6 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* mb/google/geralt: Create variant CiriRuihai Zhou2023-11-162-1/+8
| | | | | | | | | | | | | | | | | | Create the variant Ciri and enable MAX98390 AMP for it. The panel related support will be added in the follow up CLs. BUG=b:308968270 TEST=emerge-geralt coreboot BRANCH=None Change-Id: I7bbe9ed5e722a70bab1c799a61ce38d2ad58ab25 Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78954 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* mb/intel/mtlrvp: Create mtlrvp4es_p_ext_ec variantUsha P2023-11-162-4/+10
| | | | | | | | | | | | | | | | This patch creates a new variant mtlrvp4es_p_ext_ec. The new variant will support ESx samples. The existing mtlrvp_p_ext_ec variant will support the QS samples. BUG=b:310775573 TEST= Build and boot mtlrvp4es_p_ext_ec. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: Iad72c0f6343af149d16d8b1f8639ba496f6aab0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/79052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* lib: Update locales for non-VBOOT platformsSubrata Banik2023-11-161-8/+10
| | | | | | | | | | | | | | | | | | This patch sets the default locales to English for platforms that do not have support for VBOOT configuration. This ensures that the system will use English locales if the platform does not provide its own locale settings. TEST=Built and booted the google/rex platform successfully. Change-Id: I7554c8bfd58411f460deeb22cf7218059ca8ba9f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79054 Reviewed-by: Hsuan-ting Chen <roccochen@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
* mb/google/brya/var/osiris: Update power limit values for RPL CPUDavid Wu2023-11-161-0/+6
| | | | | | | | | | | | | | | | | Update power limit values based on the suggestion of the thermal team for RPL CPU. The PL1 value (28W) suggested by the thermal team which is different from the reference document 686872 (PL1=15W). BUG=b:310834985 TEST=built and booted into OS. Change-Id: Ia2540ecd1fc453701b9160c97d82ba50b88ee848 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79059 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* acpi/acpigen: drop len assert in acpigen_pop_lenFelix Held2023-11-151-2/+0
| | | | | | | | | | | | This is already handled as a separate case in the code below, so there's no need for this assert any more. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7511ec5683a924dc289faa2b9fabd0e8714d291e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* acpi/acpigen: introduce and use ACPIGEN_RSVD_PKGLEN_BYTESFelix Held2023-11-151-14/+12
| | | | | | | | | | | Use a define instead of magic numbers. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2c6d17bd78a0e207f9130102b43ba78aa55ce377 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* acpi/acpigen: rework acpigen_pop_len for different size PkgLengthFelix Held2023-11-151-6/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously acpigen_pop_len always wrote a 3 byte PkgLength to the 3 bytes reserved by acpigen_write_len_f. After this patch acpigen_pop_len encodes PkgLength in 1-3 bytes depending on the PkgLength. When less than the 3 bytes that were previously reserved in the corresponding acpigen_write_len_f call are needed for PkgLength, the payload data will be moved back by the number of reserved bytes that aren't needed for the PkgLength. This fixes the problem that the Windows AML parser doesn't like a 3 byte PkgLength being used for the size of the buffer containing UTF-16 strings when the length could be encoded in a single PkgLength byte. In that case, Windows previously ignored the whole SSDT containing this larger than necessary PkgLength encoding. It should however be noted that the ACPI 6.4 spec doesn't specify if it's required to always use the most compact possible encoding of the PkgLength or not. Since iasl generates the shortest possible PkgLength encoding, it's also a good idea to make coreboot's acpigen do the same although it's not required by the specification. With this patch applied, Windows still boots on Mandolin and the time it takes to write the tables doesn't change. To measure the times, the log level in bs_sample_time was increased to BIOS_CRIT and the console log level was increased to BIOS_CRIT too to only get those times as output. BS: BS_WRITE_TABLES run times (exec / console): 8 / 0 ms Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib897b08a05a7cdc52902d51364246c260ea1f206 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
* soc/amd/genoa: Add mmio.aslVarshit Pandya2023-11-152-0/+407
| | | | | | | | | | | | This patch adds asl code for MMIO device like I2C, UART, GPIO etc. Change-Id: Ic5bc2cc0141e9da7e2c6ed7691188d7c94b6b1e3 Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>t show Reviewed-on: https://review.coreboot.org/c/coreboot/+/78895 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/pirika: Add support for new memory CXMT CXDB4CBAM-ML-ADaniel_Peng2023-11-153-2/+5
| | | | | | | | | | | | | | | | | | | | | | Add support for the new memory CXMT CXDB4CBAM-ML-A. BUG=b:304932936 BRANCH=firmware-dedede-13606.B TEST=Run command "go run \ ./util/spd_tools/src/part_id_gen/part_id_gen.go \ JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ \ src/mainboard/google/dedede/variants/pirika/memory/\ mem_parts_used.txt" And confirm the mainboard boot normally with CXMT CXDB4CBAM-ML-A memory. Change-Id: Iff2ed16bcbc9b0755e60a284246aa928625fa26a Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78892 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* soc/qualcomm/{sc7180,sc7280}: Use correct return types for functionsZebreus2023-11-152-6/+6
| | | | | | | | | | | | | Some functions in the headers for sc7180 and sc7280 specified the int as their return type when they should have used enum cb_err. Found while testing GCC 13.2.0 Change-Id: I41331fe708a396f7f2f40359e8ba03c8a46a4d4b Signed-off-by: Zebreus <lennarteichhorn@googlemail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Julius Werner <jwerner@chromium.org>
* arch/arm64: Avoid GCC warning about out of bounds array accessZebreus2023-11-151-1/+1
| | | | | | | | | | | | | With the update to GCC 13 a new warning about subtracting numbers from arrays appears. src/arch/arm64/armv8/mmu.c:296:9: error: array subscript -1 is outside array bounds of 'u8[]' {aka 'unsigned char[]'} [-Werror=array-bounds=] Change-Id: I4757ca2e7ad3f969d7416041ea40c3e9866cdf49 Signed-off-by: Zebreus <lennarteichhorn@googlemail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79014 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cannonlake: Drop entries from soc_acpi_name()Matt DeVillier2023-11-141-2/+0
| | | | | | | | | | | | | | | | | | The THRM and SATA PCI devices do not currently have any ACPI devices defined, so drop them from soc_acpi_name() so they do not end up in the LPI constraint list. This eliminates the following errors under Linux: AE_NOT_FOUND: _SB_.PCI0.THRM AE_NOT_FOUND: _SB_.PCI0.SATA TEST= build/boot google/hatch (jinlon) and verify no ACPI errors. Change-Id: I3827b152644e2eaecc1ad288d441d2dad4d76ccb Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79013 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nb/intel/sandybridge: Drop raminit_native.hKeith Hui2023-11-144-14/+1
| | | | | | | | | | | | | After commit adaeb1102186 (nb/intel/sandybridge: Clean up post Haswell SPD mapping API migration), no boards use this header anymore and it no longer offers original content. Adjust northbridge code #includes as needed and drop it. Change-Id: I2785e920bd6188dbfc1a6157351083ec4a2526d0 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* mb/apple/macbookair4_2: Drop obsolete spd.bin fileKeith Hui2023-11-141-0/+0
| | | | | | | | | | | | After commit 940fe080bf1e (mb/apple/macbookair4_2: Correctly implement SPD mapping the Haswell way), this file is obsolete and can be removed. Change-Id: I5afe6809c7097ab8529a3c1ec7befbd0d6f01c5f Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* mb/lenovo/t530/early_init.c: Drop unused and revise used includesKeith Hui2023-11-141-3/+1
| | | | | | | | | | | | | | | | | With commit adaeb1102186 (nb/intel/sandybridge: Clean up post Haswell SPD mapping API migration), raminit_native.h now only includes 4 other headers and offers no original content. Based on the idea that all source files should include what they use directly, drop it in favor of sandybridge.h (which it already includes anyway) and types.h (replacing stdint.h because it also uses boolean constructs). Board appears to not use anything sb/intel/bd82x6x/pch.h provides. And the board still builds after dropping it. Change-Id: I1b201fe4dd29bac5feb08f372d1e36353eac161d Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78783 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brox: Set unstuffed straps to NCShelley Chen2023-11-141-15/+15
| | | | | | | | | | | | | | | All of these signals have net names, but are actually unstuffed, so we have to set them to NC. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I27d8b7cd02aefb49a2dc031a30eb0d1e8aa9faa9 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* cpu/intel/model_2065x: Read CPU voltage for SMBIOSPatrick Rudolph2023-11-141-0/+1
| | | | | | | | | | | | Report smbios_cpu_get_voltage() on Sandy Bridge as well. Change-Id: I13ea930a58eaedc24d69fa3790f1f2a151558a80 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78432 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cmn/block/cse: Support sending EOP from payloadKapil Porwal2023-11-143-1/+22
| | | | | | | | | | | | | | Skip sending EOP from coreboot when payload is sending it. BUG=b:279184514 TEST=Verify sending EOP from depthcharge on google/rex Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I0fbb9fd0f8522eefad39960ca3167c2ba764f523 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74765 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/eve: Make use of the chipset devicetreeFelix Singer2023-11-141-53/+26
| | | | | | | | | | | Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: I866250602701e7e83a695d346f4b404b1bbae6d5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
* mb/google/glados: Make use of the chipset devicetreeFelix Singer2023-11-148-102/+71
| | | | | | | | | | | Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: I4f2c4f4a576ea2fd2ccb7a7e6b52cf258bac5f84 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79043 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/protectli/vault_kbl: Make use of the chipset devicetreeFelix Singer2023-11-131-50/+15
| | | | | | | | | | | Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: Ie25c56f48648733095ab9d2a565c842b2f90efb2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79041 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/kontron/bsl6: Make use of the chipset devicetreeFelix Singer2023-11-133-29/+24
| | | | | | | | | | | Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: Ic25d112a95903e77b58bda70bbcc3f08df383395 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/purism/librem_skl: Make use of the chipset devicetreeFelix Singer2023-11-132-35/+14
| | | | | | | | | | | Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: If4f89fb81664474e03ab0ade76cfbd617127127e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79040 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/intel/kunimitsu: Make use of the chipset devicetreeFelix Singer2023-11-131-51/+24
| | | | | | | | | | | Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: I413a3630bda841ae9ed6c4a584d2250a81c28308 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
* mb/intel/saddlebrook: Make use of the chipset devicetreeFelix Singer2023-11-131-46/+21
| | | | | | | | | | | Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: Ic4043828baf43d14f7f2060fa3946e3a9e2008fc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79038 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/acer/aspire_vn7_572g: Make use of the chipset devicetreeFelix Singer2023-11-131-11/+8
| | | | | | | | | | | | | | | | The comments related to the PCI devices are superfluous since the reference names from the chipset devicetree are used. So remove the comments and also the devices which are turned off, or in general have an equal state compared to the configuration in chipset devicetree. Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: Ic45446b03a3c571837fc1c41f55d60bdf2a25a7e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
* mb/facebook/monolith: Make use of the chipset devicetreeFelix Singer2023-11-131-22/+19
| | | | | | | | | | | Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: Ib1adeaf4745804dfc91f99fb4e4491b68631202c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-20 12:15:36 +0000