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* nb/intel/x4x: Reset DQS probe on all channelsAngel Pons2021-01-151-5/+7
* nb/intel/pineview: Extract HPET setup and delay functionAngel Pons2021-01-157-50/+62
* vc/eltan/security/verified_boot/vboot_check.c: Add check PROG_POSTCARFrans Hendriks2021-01-151-1/+6
* mb/facebook/fbg1701/Kconfig: Remove dependency for USE_VENDORCODE_ELTANFrans Hendriks2021-01-151-1/+0
* mb/google/asurada: Implement HW reset functionYidi Lin2021-01-151-0/+4
* soc/amd/cezanne,picasso/uart: remove unneeded struct nameFelix Held2021-01-152-2/+2
* mainboard/volteer: Configure UsbTcPortEn valueBrandon Breitenstein2021-01-141-8/+1
* soc/intel/tgl: Add configurable value for UsbTcPortEnBrandon Breitenstein2021-01-142-0/+8
* soc/amd/picasso: Remove printf in aslRaul E Rangel2021-01-142-26/+0
* build system: Structure and serialize INTERMEDIATEPatrick Georgi2021-01-1410-44/+14
* soc/amd/picasso/uart: add missing device/device.h includeFelix Held2021-01-141-0/+1
* soc/amd/cezanne: add remaining non-ACPI parts of UART supportFelix Held2021-01-141-0/+35
* soc/amd/cezanne: add AOAC supportFelix Held2021-01-145-1/+77
* mb/amd/majolica: use integrated UART as consoleFelix Held2021-01-141-0/+1
* soc/amd/cezanne: add console UART supportFelix Held2021-01-147-0/+87
* soc/amd/stoneyridge: use SOC_AMD_COMMON_BLOCK_UARTFelix Held2021-01-145-28/+11
* soc/amd/common/block/uart/Makefile: use all targetFelix Held2021-01-141-7/+1
* soc/amd/piasso/uart: move get_uart_base prototype to common code headerFelix Held2021-01-144-3/+12
* soc/amd/common/uart: move CONSOLE_UART_BASE_ADDRESS back to SoC codeFelix Held2021-01-142-14/+8
* soc/amd/picasso: remove broken and unused legacy UART supportFelix Held2021-01-144-99/+1
* mb/google/dedede/var/boten: Support ELAN i2c-hid touchscreen for botenflexStanley Wu2021-01-141-0/+20
* soc/amd/picasso: Disable CBFS MCACHERaul E Rangel2021-01-131-0/+1
* sb/intel: Add CBMC entries in GNVSKyösti Mälkki2021-01-1310-5/+20
* cpu/x86/smm: Pass GNVS with smm_module_loader v2Kyösti Mälkki2021-01-131-0/+2
* ACPI: Have single call-site for acpi_inject_nvsa()Kyösti Mälkki2021-01-1322-102/+4
* mb/google/kahlee,zork: Use mainboard_fill_gnvs()Kyösti Mälkki2021-01-134-28/+24
* ACPI: Add common acpi_fill_gnvs()Kyösti Mälkki2021-01-1317-87/+14
* soc/amd: Rename to soc_fill_gnvs()Kyösti Mälkki2021-01-133-30/+13
* soc/amd: Rename to pm_fill_gnvs()Kyösti Mälkki2021-01-134-13/+9
* mb/google/volteer/variants/delbin: Update PL1 min and max for DelbinDeepika Punyamurtula2021-01-131-5/+5
* sb/intel/bd82x6x: Correct xHCI sleep workaroundAngel Pons2021-01-132-43/+77
* mb/google/volteer: Add CSE Lite SKU support to Copanohao_chou2021-01-131-0/+1
* soc/intel/tigerlake: Disable TC cold supportSrinidhi N Kaushik2021-01-131-0/+3
* soc/intel: rename uart_max_indexMichael Niewöhner2021-01-129-10/+10
* mb/google/brya: Initialize overridetree.cbEric Lai2021-01-122-0/+300
* mb/google/brya: Add gpio tableEric Lai2021-01-121-2/+371
* mb/google/volteer: Configure Voxel USB2 ports for Type CJohn Zhao2021-01-121-0/+3
* soc/intel/denverton_ns: Drop redundant `DEFAULT_ACPI_BASE`Angel Pons2021-01-122-2/+1
* cpu/x86/sipi_vector: Simplify loop getting unique CPU numberPatrick Rudolph2021-01-121-3/+2
* device/pci_device.c: Use same indents for switch/caseFelix Singer2021-01-121-1/+1
* soc/intel/common/pcie: Add helper function for getting mask of enabled portsFurquan Shaikh2021-01-123-0/+58
* device: Use __pci_0_00_0_config in config_of_soc()Furquan Shaikh2021-01-121-5/+6
* soc/intel/alderlake: Add PCH ID 0x5182Subrata Banik2021-01-123-1/+4
* drivers/genesyslogic/gl9763e: Add HS400ES compatibility settingsBen Chuang2021-01-122-0/+9
* mb/google/zork/var/vilboz: Fix FW_CONFIG_SHIFT_WWAN valueJohn Su2021-01-121-1/+1
* cpu/intel/haswell: Add delay for TPM before Flex Ratio rebootAngel Pons2021-01-111-0/+5
* cpu/intel/haswell: Allow tuning VR for C-state operationsAngel Pons2021-01-112-2/+50
* cpu/intel/haswell: Raise PSI1 threshold to 20AAngel Pons2021-01-111-1/+1
* cpu/intel/haswell: Enable turbo ratio if availableAngel Pons2021-01-111-4/+7
* cpu/intel/haswell: Do not set PMG_IO_CAPTURE_BASE MSRAngel Pons2021-01-111-6/+0
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