| Commit message (Collapse) | Author | Age | Files | Lines |
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- Add support for edp aux read and write.
- Update edp panel properties based on edid read.
- Configure edp controller and edp phy.
Panel details:
Manufacturer: SHP Model 1523 Serial Number 0
Made week 53 of 2020
EDID version: 1.4
Digital display
8 bits per primary color channel
DisplayPort interface
Maximum image size: 31 cm x 17 cm
Gamma: 220%
Check DPMS levels
Supported color formats: RGB 4:4:4
Default (sRGB) color space is primary color space
First detailed timing is preferred timing
Supports GTF timings within operating range
Established timings supported:
Standard timings supported:
Detailed timings
Hex of detail: 5a8780a070384d403020350035ae10000018
Detailed mode (IN HEX): Clock 346500 KHz, 135 mm x ae mm
0780 07b0 07d0 0820 hborder 0
0438 043b 0440 0485 vborder 0
-hsync -vsync
Did detailed timing
Hex of detail: 653880a070384d403020350035ae10000018
Detailed mode (IN HEX): Clock 144370 KHz, 135 mm x ae mm
0780 07b0 07d0 0820 hborder 0
0438 043b 0440 0485 vborder 0
-hsync -vsync
Hex of detail: 000000fd003090a7a7230100000000000000
Monitor ranges (bare limits): 48-144Hz V, 167-167kHz H, max dotclock
350MHz
Hex of detail: 000000fc004c513134304d314a5734390a20
Monitor name: LQ140M1JW49
Changes in V2:
- Remove Misc delays in edp code.
- Move mdss soc code to disp.c
- Update EDID read using I2C write & read.
Changes in V3:
- Remove unrelated delays.
- Misc changes.
BUG=b:182963902,b:216687885
TEST=Validated on qualcomm sc7280 development board.
Monitor name: LQ140M1JW49
Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com>
Change-Id: If89abb76028766b19450e756889a5d7776106f95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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This patch adds a function to calculate best rational approximation
for a given fraction and unit tests for it.
Change-Id: I2272d9bb31cde54e65721f95662b80754eee50c2
Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66010
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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A DDR5 DIMM internally has two channels each of width 32 bit.
But the total physical channel width is 64 bit.
BUG=b:180458099
TEST=Boot DDR5 to kernel
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: Ic5e9c58f255bdf86a68ce90a4f853bf4e7c7ccfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52730
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Enable I2C2 and register touchscreen ACPI device for pirika.
BUG=b:236564261
TEST=touch screen is functional.
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Id2fd5606b7126eabc1c88bf516198ff00b5d75dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Follow latest schematic, GPP_A17 is used to enable AMP power.
BUG=b:240006200
BRANCH=firmware-brya-14505.B
TEST=Check I2C scan can see the AMP return ACK.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ia6c52302a12ddec68303714ac07e96a65a8f8fb8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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Use the new "detect" method instead of "probed". Fixes an uncommon issue
where i2c-hid fails to initialize the device on Linux.
Tested on: gaze15, gaze16-3060, lemp10, oryp8
Tested:
- Linux: Touchpad works across 50 reboots
- Windows: Touchpad is still detected as an I2C HID device
- Windows: Extra I2C HID devices are not shown in Device Manager
Change-Id: I6a899c64a6d77b65a2ae57ab8df81cd84b568184
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Initialize SPI bus 0 for Chrome EC control.
TEST=build pass
BUG=b:236331724
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I6de5ea8a0273a3b0c725e4cdbcf69f4db74c5db7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Copy the constraint from ADL-S to ADL-P.
Fixes the following warning in Linux on System76 oryp9, which has an
NVIDIA GPU on the bridge.
pcieport 0000:00:01.0: can't derive routing for PCI INT A
This, in turn, resolves an IRQ conflict with the PCH HDA device that
would cause a stack track on every boot.
irq 10: nobody cared (try booting with the "irqpoll" option)
<snip>
[<00000000bf549647>] azx_interrupt [snd_hda_codec]
Disabling IRQ #10
Change-Id: I550c80105ff861d051170ed748149aeb25a545db
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66285
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure eMMC DLL tuning values for Craask board.
BUG=b:238985924
TEST="Use the value to boot on Nivviks and Craask successfully."
Change-Id: I14f3e2329404cca94e14034d1fb52fcb99a2ddc9
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66218
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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The first CSE Lite SKU is available, therefore enable the Kconfig
option to have the CSE reboot the system into its RW FW during a cold
boot.
BUG=b:240228892
TEST=TBD
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I00ef4176cf08cbeed06e446cfe68f06cb1ea27b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66287
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch calls into vboot API (vb2api_get_fw_boot_info) to retrieve
FW slot boot information like (tries count, current boot slot, previous
boot slot, previous boot status and boot mode).
Upon retrieval of the vboot information, elog callback from ramstage
records the info into the eventlog.
Additionally, this patch refactors the existing event logging mechanism
to add newer APIs to record vboot firmware boot related information.
BUG=b:215615970
TEST=Build and boot google/kano to ChromeOS and run below command to
check the cbmem log:
Scenario 1:
localhost ~ # cbmem -c | grep VB2
[INFO ] VB2:vb2_check_recovery() Recovery reason from previous boot:
0x0 / 0x0
[INFO ] VB2:vb2api_fill_boot_config() boot_mode=`Developer boot`
VB2:vb2api_get_fw_boot_info() fw_tried=`A` fw_try_count=0
fw_prev_tried=`A` fw_prev_result=`Success`.
....
Scenario 2:
localhost ~ # crossystem recovery_request=1
localhost ~ # cbmem -c | grep VB2
[INFO ] VB2:vb2api_fill_boot_config() boot_mode=`Manual recovery boot`
VB2:vb2api_fill_boot_config() recovery_reason=0x13 / 0x00
VB2:vb2api_get_fw_boot_info() fw_tried=`A` fw_try_count=0
fw_prev_tried=`A` fw_prev_result=`Unknown`.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6882cd1c4dbe5e24f6460388cd1af4e4a05fc4da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65561
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add static check to ensure the reserved APOB DRAM space is the same size
as the MRC_CACHE region specified in the fmap.
Update sabrina APOB DRAM size to match the fmap.
TEST: Timeless builds identical. Test build with a larger MRC_CACHE than
APOB DRAM failed the assert as expected.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ia14f6ef94b9062df0612fe96098b1012085ccf9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65878
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In order to pass PCIe base address to payloads, implement pcie_fill_lb()
to fill coreboot table with PCIe info.
BUG=b:182963902,b:216686574,b:181098581
TEST=Verified on Qualcomm sc7280 development board with NVMe endpoint
(Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is
getting detected in response to 'storage init' command in depthcharge
CLI prompt.
Output logs:
->dpch: storage init
Initializing NVMe controller 1e0f:0001
Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY
Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0
* 0: NVMe Namespace 1
1 devices total
Also verified NVMe boot path that is depthcharge is able to load the
kernel image from NVMe storage.
Change-Id: I1ca2be55b98c8d1b86576072078cdda02ac55940
Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57614
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add PCIe domain support for herobrine by enabling it in the devicetree.
BUG=b:182963902,b:216686574,b:181098581
TEST=Verified on Qualcomm sc7280 development board with NVMe card
(Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is
getting detected in response to 'storage init' command in depthcharge
CLI prompt.
Output logs:
->dpch: storage init
Initializing NVMe controller 1e0f:0001
Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY
Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0
* 0: NVMe Namespace 1
1 devices total
Also verified NVMe boot path, that is depthcharge is able to load the
kernel image from NVMe storage.
Change-Id: Ied8fbbc8d20698ee081d93ba184b7d0291bb6a76
Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65137
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable PCIe functionality on sc7280 and supply all the needed data
for PCIe generic platform driver.
BUG=b:182963902,b:216686574,b:181098581
TEST=Verified on Qualcomm sc7280 development board with NVMe card
(Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is
getting detected in response to 'storage init' command in depthcharge
CLI prompt.
Output logs:
->dpch: storage init
Initializing NVMe controller 1e0f:0001
Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY
Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0
* 0: NVMe Namespace 1
1 devices total
Also verified NVMe boot path, that is depthcharge is able to load the
kernel image from NVMe storage.
Change-Id: I1f79a0ae2dea594d6026d55a15978eeb92a8ff18
Signed-off-by: Prasad Malisetty <quic_pmaliset@quicinc.com>
Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66148
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Disabling the Package C-state demotion feature for brya baseboard
as a work around to the S0ix issue and also this doesn't have any
impact on the power and performance measured and verified by the
PNP team.
This feature will be enabled after its functionality is verified with no
issues and also based on its impact on PNP.
BUG=none
BRANCH=firmware-brya-14505.B
TEST=Boot and verified that S0ix issue is resolved.
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Change-Id: Id3941c8870d41b25488c8ac5d38534fa94664d4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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This adds SPDX-License-Identifiers to all of the files in src/include
that are missing them or have unrecognized identifiers.
Files that were written specifically for coreboot and don't have license
information are licensed GPL-2.0-only, which is the license for the
overall coreboot project.
Files that were sourced from Linux are similarly GPL-2.0-only.
The cpu/power files were committed with source that was licensed as
GPL-2.0-or-later, so presumably that's the license for that entire
commit.
The final file, vbe.h gives a pointer to the BSD-2-Clause license
at opensource.org.
Change-Id: I3f8fd7848ce11c1a0060e05903fb17a7583b4725
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Sabrina"
This reverts commit 78261e308de5361b2ff045091e8fb18cad2a5035.
Reason for revert: Now that PSP supports a soft fuse flag to toggle the
verstage serial logs, prevent PSP verstage from writing to the UART.
BUG=None
TEST=Build and boot to OS in Skyrim with PSP verstage. Ensure that PSP
verstage logs are not seen twice in the console.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I7ef2d585c320ea5903197939136dd2049a71af95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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HW Modexp engine is verified to be working fine. Any verification
failures during PSP verstage are because the firmware body is not read
correctly. This might be because of the incorrect SPI ROM mapping. Hence
enable the HW modexp engine for keyblock, preamble and firmware body
verification.
BUG=b:240175446
TEST=Build and boot to OS in Skyrim with PSP verstage using one of the
FW slots.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I8f6742630a7049354a24053fce28c477e53259e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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clang shows the warning below:
src/drivers/elog/elog.c:171:13: error:
format string is not a string literal
(potentially insecure) [-Werror,-Wformat-security]
elog_debug(msg);
^~~
Found-by: clang (13.0.1)
Change-Id: I3f8949f9ce0c4ef4823530c61c503b0883bb5efc
Signed-off-by: Matei Dibu <matdibu@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66262
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Add PCIe platform driver for Qualcomm platforms.
Reference:
- linux/drivers/pci/controller/dwc/pcie-qcom.c
- Linux driver base commit: 82a823833f4e3769e82cdb4df1bc2234bc65b16c
BUG=b:182963902,b:216686574,b:181098581
TEST=Verified on Qualcomm sc7280 development board with NVMe card
(Koixa NVMe, Model-KBG40ZPZ256G with FW AEGA0102). Confirmed NVMe is
getting detected in response to 'storage init' command in depthcharge
CLI prompt.
Output logs:
->dpch: storage init
Initializing NVMe controller 1e0f:0001
Identified NVMe model KBG40ZPZ256G TOSHIBA MEMORY
Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0
* 0: NVMe Namespace 1
1 devices total
Also verified NVMe boot path, that is depthcharge is able to load the
kernel image from NVMe storage.
Change-Id: Iccf60aa56541f5230fa9c3f821d7709615c36631
Signed-off-by: Prasad Malisetty <quic_pmaliset@quicinc.com>
Signed-off-by: Veerabhadrarao Badiganti <quic_vbadigan@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53902
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fix the license in header file.
BUG=none
BRANCH=firmware-brya-14505.B
TEST=none
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I025f7c571d09e4cc63a659279e63d17c098c01cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
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- Move configs for PCIe ports not present on z220_sff_workstation
from the devicetree.cb of base board to the overridetree.cb of
z220_cmt_workstation.
- Add a note for ME/AMT Flash Override jumper, for it is hard to
flash from OEM firmware either internally or externally without
closing this jumper.
- Add a side note for similar HP Compaq Elite 8300 SFF.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I35d8b97f52a83910a61c12b1f7367ee7a19a9ad7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65703
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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DPTF Policy and temperature sensor values from thermal team.
BUG=b:236294162
TEST=emerge-brask coreboot
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Iebcfb74c4bc719e6d8d8d9317435becd912eaf85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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futility now supports image truncation and signing of whole images with
a single command invocation. Use it for vboot-enabled coreboot images.
TEST=Build and run coreboot on google/volteer
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I49eb7e977b635ccb9f6c1b76e53c36e82be1d795
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Change-Id: I30bbd0288475fbefec55ce294e7963df1de6aa6a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
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Change-Id: I21b954ce62259bb77d88775c3086cfac17dd90c7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
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Replace `LNotEqual(a, b)` with `a != b`.
Change-Id: If0e9fcea680d487c28a965e944b3333bb5a07026
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60696
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace `LLess(a, b)` with `a < b`.
Change-Id: Ief1d069ae0fb19a2179f08c2e9cf416367661e69
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60674
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace `Add (a, b, c)` with `c = a + b`.
Change-Id: If848d391e5ec33ebfb08515414739dbdd5011e08
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
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This patch enables display port configuration as per the Rex
schematics.
TEST=Able to dump FSP UPD to ensure the override is successful.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I9e81d037416e46e52cb72344425d6d8725dae192
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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Pujjoflex support OZ711LV2LN SD card controller,
Select the Bayhub LV2 driver for OZ711LV2LN SD card.
BUG=b:215487382
TEST=Build FW and checking SD card work as expected in OS.
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I6759fde1eaf24599a1fdb364d6e78f4e4e12f311
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Create RAM IDs for:
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
MT62F1G32D2DS-026 WT:B 1 (0001)
MT62F2G32D4DS-026 WT:B 2 (0010)
BUG=b:240289148
TEST=emerge-rex coreboot
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: Ib24e07bca363984db3484aa500f7d6ea4817e517
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
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The gpios and the tick delay register are different between MT8188
and previous MediaTek SoCs, so we need to add this patch to support
SPI.
TEST=build pass
BUG=b:236331724
Signed-off-by: Liya Li <ot_liya.li@mediatek.corp-partner.google.com>
Change-Id: I6065b9d285dfd36c191f274f500fdb694920276e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66185
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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MT8188 SPI tick delay setting is moved to `spi_cmd_reg` register which
is different from previous SoCs, so we define a macro to get the
designated register.
TEST=build pass.
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia30e94a8688c0e1c1d4b3d15206f28e5bd8c9bd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66184
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TEST=build pass.
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I869c0879d09e00cf66882adb728c9ccb6ac57e03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66183
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TEST=build pass.
BUG=b:233720142
Signed-off-by: Song Fan <ot_song.fan@mediatek.corp-partner.google.com>
Change-Id: Ic300b70a38ac204b098ca9ab15cf7045b66fd76d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66182
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add RTC header file for SoC-specific settings. Add RTC support in
romstage.
TEST=build pass.
BUG=b:233720142
Signed-off-by: Song Fan <ot_song.fan@mediatek.corp-partner.google.com>
Change-Id: I38115ce0c9a4e1c1b2b7c8e6d40f47e99f7f86b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66181
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move the common definitions to rtc_reg_common.h, so we can reuse those
definitions on MT8188.
TEST=build pass
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia1d916a88b7cb875b35ee5813b7b52d9e98f5009
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66180
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TEST=get voltage as 340mV for channel 0 in MTK EVB.
BUG=b:233720142
Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com>
Change-Id: Idd1edcce6cb62fcf6991bb9342c409150989c5ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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The AUXADC register definitions are the same for all MediaTek SoCs, so
we move struct mtk_auxadc_regs to auxadc_common.h.
TEST=build pass.
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I48978a93137a7de42f8ea2873be3130cb8f534f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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This patch override `CnviBtCore` FSP UPD.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I90c9b360969aada0b0e031d62b48476fac5cee0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Add CS42L42 support in device tree.
BUG=b:240006200
BRANCH=firmware-brya-14505.B
TEST=Check cs42l42 driver can probe successfully in kernel.
cs42l42 i2c-10134242:00: Cirrus Logic CS42L42, Revision: B1
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I861f47c12f4cebb016a4cfbe225f97d34d55e233
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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Remove the parameter and set I2C bus speed to fast. Will fill the
tuning value after real tuning.
BUG=b:240006200
BRANCH=firmware-brya-14505.B
TEST=build passed.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Iba7fe4551959617ecfa49719c1124bf85d624c31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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Create the gaelin variant of the brask reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:239514438
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_GAELIN
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Change-Id: I7f1ff8690c7c57f8960e004d0490d5cede8667f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
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Add TDP and Power Limit settings for ADL-S 8+8 150W, 4+0 and 2+0.
The System Agent PCI IDs were not present in older 2.1 revision of
DOC #619501. Now that the mapping of these IDs to SKUs is known, fill
the missing TDPs and Power Limit settings based on DOC #626343.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I23dd8478e60bcc81a1048f2f6e6717dd281d1a69
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Add missing System Agent PCI IDs for ADL-S 4+0 and 2+0 to configure
VccIn Aux Imon IccMax. They were not present in older 2.1 revision of
DOC #619501. Based on DOC #619501 rev 2.6.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Idfd57ce9b63db5d5fcc9d4efb8aa27ed7cc6222d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Based on DOC #619501, #634885, #626343.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ib50db521e4d127a773f903b45d4bec5c5cc180d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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The patch updates platform_is_resuming() API such that platform resume
state is determined from the saved state (CBMEM) instead of checking PMC
registers (PM1_STS & PM1_CNT) as they are getting cleared (before/early)
ramstage.
coreboot sends DISCONNECT IPC command which times out during resume (S3)
if system has servoV4 connected on port0. The issue occurs only during
the first cycle of resume (S3) test cycle after cold boot due to side
effect of platform_is_resuming() API that is not determining the resume
(S3) state correctly in ramstage.
PM1_STS and PM1_CNT register gets cleared at the start of ramstage.
platform_is_resuming() function was checks the cleared register value
and fails the condition of resume (S3) resulting in sending DISCONNECT
IPC command. Checking the platform resume state from the CBMEM saved
state using acpe_get_sleep_type() function helps cross verify the
system previous state at the later part of ramstage.
localhost ~ # cbmem -c | grep ERROR
[ERROR] EC returned error result code 3
[ERROR] PMC IPC timeout after 1000 ms
[ERROR] PMC IPC command 0x200a7 failed
[ERROR] pmc_send_ipc_cmd failed
[ERROR] Failed to setup port:0 to initial state
[ERROR] PMC IPC timeout after 1000 ms
[ERROR] PMC IPC command 0x200a7 failed
[ERROR] pmc_send_ipc_cmd failed
[ERROR] Failed to setup port:1 to initial state
[ERROR] GENERIC: 0.0 missing read_resources
[ERROR] PMC IPC timeout after 1000 ms
[ERROR] PMC IPC command 0xd0 failed
[ERROR] PMC: Failed sending PCI Enumeration Done Command
BUG=b:227289581
TEST=Verified system boots to OS and verified below tests on
Redrix (ADL-P) and Nivviks (ADL-N)
1. coreboot doesn't send the DISCONNECT during S3 resume
2. suspend S3 passes with both suzyq and servoV4 connected
3. After S3 resume, system detects the pen drive with Superspeed
4. After system resumes from S3, hot-plug the pen drive, system detects
the pen drive
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I353ab49073bc4b5288943e19a75efa04bd809227
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66126
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add weida touchscreen support for drawcia.
BRANCH=dedede
TEST=Build and verify that touchscreen works on drawcia.
Change-Id: Ic76f3529771c6eeeafef7ca50fc400065aac2211
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65471
Reviewed-by: Ivan Chen <yulunchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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