summaryrefslogtreecommitdiffstats
path: root/util/amdfwtool
Commit message (Collapse)AuthorAgeFilesLines
* util/amdfwtool: Support PSP whitelist file on recovery A/B layoutKarthikeyan Ramasubramanian2022-08-011-1/+1
| | | | | | | | | | | | | | | | This is required to enable PSP verstage on SoCs with recovery A/B layout. BUG=b:217414563 TEST=Ensure that the concerned type 0x3a PSP entry is present in PSP L2 directory. Build and boot to OS in Skyrim with both PSP and x86 verstage. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I5fae2b5dbcc95a99af3df9f59bb8516280ec1281 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* util/amdfwtool: Update the location of PSP verstage and signing keyKarthikeyan Ramasubramanian2022-07-261-2/+2
| | | | | | | | | | | | | | | On SoCs which use A/B recovery layout, PSP verstage and signing keys are expected to be present only in PSP L2 directory. Update amdfwtool to include the PSP verstage and signing key only in PSP L2 directory. BUG=b:239519603, b:238938623 TEST=Build and boot to OS in Skyrim with PSP verstage. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ieeb415be800b7ccf10d6983eb0b567e0a5eaa955 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* util/amdfwtool: Initalize all variables before useFred Reitberger2022-06-301-12/+1
| | | | | | | | | | | | | | | | Not all of the fields of the amd_cb_config structure were properly initialized. Rather than initialize each field individually, initialize the entire structure to 0. TEST: Boot chausie Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ia343f01bce3956d66d01ce485b43963193c9df31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* util/amdfwtool: Add amdfwread utilityRobert Zieba2022-05-135-38/+285
| | | | | | | | | | | | | | | | | | Amdfwtool creates AMD firmware images however there is currently no way to get information from an existing image. This commit adds amdfwread to support that functionality. At the moment only reading PSP soft fuse flags is supported. Example usage: `amdfwread --soft-fuse bios.bin`, example output: `Soft-fuse:0x400000030000041`. BUG=b:202397678 TEST=Ran amdfwread and verified that it correctly reads the soft fuse bits, verified that built AMD FW still boots on DUT Signed-off-by: Robert Zieba <robertzieba@google.com> Change-Id: I15fa07c9cad8e4640e9c40e5539b0dab44424850 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
* util/amdfwtool: Add IKEK key for Trusted ApplicationKarthikeyan Ramasubramanian2022-05-053-0/+5
| | | | | | | | | | | | | | | This binary file is required for use by Trusted Applications that execute in PSP. BUG=b:229947314 TEST=Build and boot to OS in Skyrim. Change-Id: I2d05792cfd98fa9c38f5deef1ac3282625983eeb Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* amdfwtool: Use command line option use-combo to decide if use comboZheng Bao2022-04-252-14/+19
| | | | | | | | | | | | The macro PSP_COMBO is removed and instead use the flag use_combo. As long as this flag is false, the amdfwtool behaves the same way as the macro does. Change-Id: Ief0d78ae1e94b8183d6cf3195935ff9774fee426 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* amdfwtool: Change the name of macros for 'BHD'Zheng Bao2022-04-252-10/+10
| | | | | | | | | | | | | Use BHD instead of BDT as the name of cookie macro. Use L2 to make it clear it is for level 2. The 'BHD2' is misleading, which is going to be used for combo entry. The definition in psp_verstage is also changed. Change-Id: Ia10ac5e873dab6db7d66e63773a7c63f504950b2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* util/amdfwtool: Maintain one copy of PSP Level2 entriesKarthikeyan Ramasubramanian2022-04-142-4/+20
| | | | | | | | | | | | | | | | | | | | | | | AMDFWtool maintains 2 copies of PSP Level2 entries - one in primary slot A (Type 0x48) and another in backup slot B (Type 0x4A). On boards which use VBOOT with 2 RW firmware slots, maintaining 2 copies of PSP Level2 entries in each FW slot is redundant and space-consuming. Introduce option to maintain only one copy of PSP Level2 entries and point to it from both slots A & B. BUG=None TEST=Build and boot to OS in Skyrim. Ensure that only one copy is added to each FW slot. This achieved a space saving of 1.5 MB in each FW slot. Before: apu/amdfw 0x415fc0 raw 3043328 none After: apu/amdfw 0x415fc0 raw 1556480 none Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I06eef8e14b9c14db1d02b621c2f7207188d86326 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* amdfwtool: Add a flag to record the second gen instead of romsigZheng Bao2022-04-132-13/+38
| | | | | | | | | | | | This is for future feature combo, which gets the soc id from fw.cfg in a loop instead of the command line, and the romsig is not set until fw.cfg is processed. Change-Id: Id50311034b46aa1791dcc10b107de4af6c86b927 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* amdfwtool: Add a macro to set explicitly second gen for old SOCsZheng Bao2022-04-052-1/+6
| | | | | | | | | | | | It is more reasonable than getting the value from memset. For the reserved bits, keep them as they were for old SOCs. Change-Id: I65caa11e835d2ff52bec4b8904057bbced434891 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* util/amdfwtool/data_parse: fix SPL table handling regressionFelix Held2022-04-031-2/+2
| | | | | | | | | | | | | Use the SPL table binary from the config file if no override is specified via the spl-table command line argument. This fixes a regression caused by commit 6c5ec8e31ccbe3d9bbf201c956fc3b54703a9767 (amdfwtool: Add options to support mainboard specific SPL table). Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I93419a878b41b1dfcbf58d930740aaae553120f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* util/amdfwtool: use ISH support for Sabrina SoCFelix Held2022-03-301-0/+11
| | | | | | | | | | | The PSP in the Sabrina SoC uses the image slot header to find the second level PSP directory table, so it needs the ISH to be generated. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9e6308854147c9f6f72d722215c833ee86ee4f94 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63186 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/amdfwtool: add Sabrina SoC typeFelix Held2022-03-301-0/+6
| | | | | | | | | | | | Add PLATFORM_SABRINA to the enum of supported platforms and integrate it into the existing code. Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ibe52b44395619f697686bd900a522562abbe7646 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* util/amdfwtool: select A/B recovery when ISH is usedFelix Held2022-03-301-4/+6
| | | | | | | | | | | | | In newer AMD SoCs, the image slot header is used in the AMD A/B recovery scheme, so set recovery_ab to true when need_ish is true. Also move the block of code before the process_config call, since that call will already use the recovery_ab field of the cb_config struct. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I65903765514f215bf5cc9b949d0b95aff781eb34 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63184 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/amdfwtool: use table-relative addressing in ISH caseFelix Held2022-03-301-1/+3
| | | | | | | | | | | When the image slot header (ISH) is used, the addresses in the PSP and BIOS directory tables need to be relative to the beginning of the table. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia61f7c8313d5a1af95c68b9177a53a2f5443552a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* amdfwtool: Clear the whole byte of EFS_GENZheng Bao2022-03-291-0/+1
| | | | | | | | Change-Id: I434e031e906f73362b1e920e034fa15a8d078ab2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* amdfwtool: Add ISH header support for A/B recovery layoutZheng Bao2022-03-274-12/+62
| | | | | | | | | | | | | | | | Image Slot Header (ISH) is a new feature. The rom layout for A/B recovery with ISH: EFS -> PSP L1 0x48 -> ISH A -> PSP L2 A -> BIOS L2 A 0x4A -> ISH B -> PSP L2 B -> BIOS L2 B The newer 55758 will updated about the boot priority and update retry in ISH header. Change-Id: Ib0690cde1dce949514c7aacebe13096b7814ceff Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* util/amdfwtool: add MSMU, SPIROM_CFG and DMCUB PSP FW typesFelix Held2022-03-273-0/+15
| | | | | | | | | | | | Compared to Cezanne, the Sabrina SoC has a 3 additional PSP firmware table entries, so add those as a preparation for Sabrina support. Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iaa5aacd53b3c7637f6d5e94b1a8d92bba57ddb9d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* amdfwtool: Change the some FW's level for A/B recoveryZheng Bao2022-03-231-3/+3
| | | | | | | | | | | | | | | | | | The Pubkey(0), PSP bootloader(1) and IKEK(0x21) should be put to level 2 only for A/B recovery for Sabrina, which is going to be the long term and A/B recovery layout only. So the amdfwtool should be changed for Sabrina. The old levels of these 3 FWs are for Cezanne, which doesn't use AB recovery now. Just set the specific field levels in generic Cezanne folder for demo. Leave the fw.cfg in Guybrush unchanged. Change-Id: I11092b52927b2c526a5be719104ba39a790b6fa8 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
* amdfwtool: Check the length of matching string before accessingZheng Bao2022-03-211-10/+21
| | | | | | | | | | | | If AB recovery is enabled and get a "Lx" in fw.cfg, wrong character is got or access violation happens. Change-Id: Ibd8ffe34fd44d860ec2115cd36117da7b02169cd Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
* amdfwtool: Clear struct match before regular expression matchingZheng Bao2022-03-091-5/+19
| | | | | | | | | | | | | | | | If it is not cleared and the number of strings is fewer than last iteration, the match[3] will keep the last value, which actually should be empty. Add assert to make sure the level is a legal value. BUG=b:222038278 Change-Id: If14e0923fbb1648d83784eb5dc1411c93227db5a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* amdfwtool: Check the real length of PMU stringZheng Bao2022-02-241-0/+3
| | | | | | | | | | | The length should be checked before the PMU_STR_INS_INDEX(th) character is accessed, otherwise it is going to an access violation. Change-Id: I8b59eb34e1cb01fd6e2571fcebc28ef2084b6ec4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* amdfwtool: Add entries for PMUI & PMUD with instance 2Zheng Bao2022-02-211-0/+4
| | | | | | | | | | Change-Id: I69c4b3cdd2473655064d1329d5319cffdba2425a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
* amdfwtool: Add support for AMD's BIOS A/B recovery featureZheng Bao2022-02-213-75/+217
| | | | | | | | | | | | | | | | | | | | | The rom layout for A/B recovery: EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A 0x4A -> PSP L2 B -> BIOS L2 B The coreboot doesn't implement the AMD's A/B recovery. This is only for the ROM layout. To save some flash space, the entire B section can be eliminated. To enable A/B recovery in PSP layout, add "--recovery-ab" to amdfwtool. TEST=Majolica(Cezanne) Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* soc/amd/*/fw.cfg: Remove the misleading name for PMUI and PMUDZheng Bao2022-02-211-30/+11
| | | | | | | | | | | Add the information of substance and instance in the string for PMUI and PMUD. It is amdfwtool's job to extract the number from the string. Change-Id: I43235fefcbff5f730efaf0a8e70b906e62cee42e Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* amdfwtool: Add options to support mainboard specific SPL tableZheng Bao2022-02-123-2/+15
| | | | | | | | | | | | | | For the generic board which uses Cezanne, we use the generic SPL table. For the Guybrush Chromebook, we need to use a customized SPL file. BUG=b:216096562 Change-Id: I385b0fe13cb78a053c07127ec3ea1c61dc42c7e4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* amdfwtool: Add SPL supportZheng Bao2022-02-073-0/+5
| | | | | | | | | | | | | | | SPL: Security Patch Level The data in SPL is used for FW anti-rollback, preventing rollback of platform level firmware to older version that are deemed vulnerable from a security point of view. BUG=b:216096562 Change-Id: I4665f2372ccd599ab835c8784da08cde5558a795 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* amdfwtool: Upgrade "relative address" to four address modesZheng Bao2021-12-162-22/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Address Mode 0: Physical Address, bit 63~56: 0x00 Address Mode 1: Relative Address to entire BIOS image, bit 63~56: 0x40 Address Mode 2: Relative Address to PSP/BIOS directory, bit 63~56: 0x80 Address Mode 3: Relative Address to slot N, bit 63~56: 0xC0 It is the expanding mode for simple relative address mode, for which address_mode equals 1. Only mode 2 is added. We need to record current table base address and calculate the offset. The ctx.current_table is zero outside the table. When it goes into the function to integrate the table, it should backup the old value and get current table base. Before it goes out the function, it should restore the value. If the table address mode is 2, the address in each entry should be also add address mode information. If not, the address mode in entry is meanless. The old mode 0,1 should be back compatible. Change-Id: I29a03f4381cd0507e2b2e3b359111e3375a73de1 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* amdfwtool: Use relative address for EFS gen2Zheng Bao2021-12-141-3/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The second generation EFS (offset 0x24[0]=0) uses "binary relative" offsets and not "x86 physical MMIO address" like gen1. The field additional_info in table header can tell if the absolute or relative address is used. Chips like Cezanne can run in both cases, so no problem comes up so far. The related change in psp_verstage has been uploaded. https://review.coreboot.org/c/coreboot/+/58316 The relative mode is the mode 1 of four address modes. The absolute mode is the mode 0. Later we will implement mode 2. Not sure if mode 3 is needed. It needs to be simple to work with psp_verstage change to make SOC Cezanne work quickly. This patch is defacto a subset of https://review.coreboot.org/c/coreboot/+/59308 which implements the framework of address mode and covers mode 0,1,2. Some hardcode value like 29 can be removed in 59308. BUG=b:188754219 Test=Majolica (Cezanne) Change-Id: I7701c7819f03586d4ecab3d744056c8c902b630f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* amdfwtool: Call the set_efs_table for StoneyridgeZheng Bao2021-11-181-7/+5
| | | | | | | | | | | | | | | | | | Related to https://review.coreboot.org/c/coreboot/+/58555 commit-id: 35b7e0a2d82ac In 58555, we added the SOC ID for Stoneyridge in amdfwtool command line. But it raised building error because it then called "set_efs_table" without setting SPI mode. So we skipped calling that. But in set_efs_table, it has case for Stoneyridge. The boards also need to have this setting. So we remove the skipping and give the proper SPI mode in mainboard Kconfig. Change-Id: I24499ff6daf7878b12b6044496f53379116c598f Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* amdfwtool: Set flag comboable as bool typeZheng Bao2021-11-181-1/+1
| | | | | | | | | | | | Fix the CL: https://review.coreboot.org/c/coreboot/+/58942 The type comboable was int but set as true. Change-Id: Id2c43378735c089a27a5aa683b55a0f7ec3677de Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59093 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* amdfwtool: Add a union for combo and psp directoryZheng Bao2021-11-182-2/+5
| | | | | | | | | | | For combo layout, this is for combo header. For non-combo layout, this is for PSP directory. Change-Id: Ie7b5aec6b511ad61972908d1d22a13aeb7dd73a9 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* amdfwtool: Set soc name for StoneyridgeZheng Bao2021-11-151-5/+7
| | | | | | | | | | | For the stoneyridge, soc_name is not set in Makefile, so set_efs_table is not called. Keep it unchanged. Change-Id: I0e82188ce64733420a578446e22a077ef789be92 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* amdfwtool: Pack out-of-bounds check into a function and moveZheng Bao2021-11-111-13/+15
| | | | | | | | | | | | Need to check the FWs number limit several times. So pack the duplicated steps into a function. And do it before access the new entry. Change-Id: I71117d1c817c0b6ddaea4ea47aea91672cc6d55a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* amdfwtool: Change the flag value to type boolZheng Bao2021-11-053-33/+33
| | | | | | | | Change-Id: I8bb87e6b16b323b26dd5b411e0063e2e9e333d05 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* amdfwtool: Fix the parameter point to NULL instead of integerZheng Bao2021-11-051-4/+4
| | | | | | | | Change-Id: Iaeeec7a7e2de7847bfcefa5b7ff3f259f86533d4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* amdfwtool: Change the definition of level to a bitwise formZheng Bao2021-11-051-4/+4
| | | | | | | | Change-Id: Icca393f0d69519cc1c3cb852a11dd7006cf72061 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* amdfwtool: Add PSP ID for combo and ISH header for A/B recoveryZheng Bao2021-10-293-15/+42
| | | | | | | | | | | | | Nobody calls the function until combo or A/B is added, so suppress the warning for now. Test=Majolica (Cezanne) Change-Id: I3082b850fb3fd2d7ae83a1c4dfd89eb7e1bd0f97 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* util/amdfwtool: rename PSP related embedded_firmware struct elementsFelix Held2021-10-192-5/+5
| | | | | | | | | | | | | | | The element at offset 0x14 in the embedded_firmware struct is the pointer to the combo PSP directory header, so rename it from comboable to combo_psp_directory to clarify that this is not a flag, but a pointer to a data structure. Also rename psp_entry to psp_directory since it points to the PSP directory table. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic6149c17ae813f4dcea71c308054849a1a2e4394 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* amdfwtool: Add an optional column of levelZheng Bao2021-09-231-6/+79
| | | | | | | | | | | | | | | | | | The value of level defined in table is the default one. We now give an extra option in config file to change this value so some FWs can be dropped in a more optimized way. For the non A/B recovery mode, The value could be L1, L2, Lb or Lx, which are level 1, leve 2, level both and using default value. If it is empty or Lx, left the level in table unchanged. Give a redundant field [12bxBX] in regular exprssion for A/B recovery which will be done later. Change-Id: I0847bc3793467a2299f14d1d2d2486f3f858d7f3 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* amdfwtool: Detect the flag multilevel to decide the actual valueZheng Bao2021-09-171-10/+16
| | | | | | | | | | | | To save the space for FW, some of the FWs are going to be defined as LVL2 entries. To be compatible to "flattened" layout, we still drop the LVL2 entry to level1 if there is only one level. Change-Id: Ibe8cdd5c14225899352b02bb19aae6059d56d428 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* amdfwtool: Add new SOC mendocinoZheng Bao2021-09-151-0/+6
| | | | | | | | Change-Id: I54492600dd954a5585ce3b1d842d264a4a50907a Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* amdfwtool: Add flag for multi FW level to the struct amd_cb_configZheng Bao2021-08-312-10/+11
| | | | | | | | | | | This change can make the code be more flexible. And later we will use amd_cb_config to transfer parameters. Change-Id: Ic726aa9fc5f67803210af71d3e9cf2438b7e2a9b Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57062 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* amdfwtool: Copy string in a safer wayZheng Bao2021-08-311-5/+10
| | | | | | | | | | | | | | The issue is reported by Coverity. Using strcpy or strcat copying string without checking length may cause overflow. BUG=b:188769921 Reported-by: Coverity (CID:1438964) Change-Id: I609d9ce405d01c57b1847a6310630ea0341e13be Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54946 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Revert "amdfwtool: Use relative address for EFS gen2"Kangheui Won2021-07-141-9/+3
| | | | | | | | | | | | | | | | This reverts commit 0fc87e31e0b9ad15dd199fe96189a2ade6abf240. Reason for revert: Breaks psp_verstage in guybrush BUG=b:182477057 Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Ie50cba4aaf31425ef8fee848c098a826f55c98da Reviewed-on: https://review.coreboot.org/c/coreboot/+/56131 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* amdfwtool: Fix the NULL pointer in parametersZheng Bao2021-07-081-1/+1
| | | | | | | | Change-Id: Ia2c65013d48fc1ad88d3caf6ef59824745c992de Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55550 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* amdfwtool: Use relative address for EFS gen2Zheng Bao2021-07-081-3/+9
| | | | | | | | | | | | | | | | | | | The second generation EFS (offset 0x24[0]=0) uses "binary relative" offsets and not "x86 physical MMIO address" like gen1. Chips like Cezanne can run in both cases, so no problem comes up so far. BUG=b:188754219 Test=Majolica (Cezanne) Change-Id: I3a54f8ce5004915a7fa407dcd7d59a64d88aad0d Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* amdfwtool: Null check the pointers before using themZheng Bao2021-06-141-2/+5
| | | | | | | | | | | BUG=b:188769922 Reported-by: Coverity (CID:1438963) Change-Id: Ia520e33c9e4065236478665fb0ef047fa47c9b81 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54999 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* amdfwtool: Add missing license headerZheng Bao2021-06-091-0/+2
| | | | | | | | Change-Id: Id466e733d421602cfe0403ead95e417f0bb37eb4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* amdfwtool: Move EFS related definitions to header fileZheng Bao2021-06-092-114/+115
| | | | | | | | | | | | | EFS: Embedded Firmware Structure These structs and macros are defined in PSP specs(#55758). They are supposed to be used by all C sources. Change-Id: I8c7ed9fa626b249b4aa48544316a941dc2625c60 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-08 05:18:39 +0000