| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | util/bucts: Clean up Makefile to match others | Martin Roth | 2021-02-25 | 1 | -4/+15 |
| | | | | | | | | | | | | | | | - Add a TARGET variable - Enable optimization and additional warnings - Add distclean target - Add help target Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I8eb190abd1ab20da7dd1ae43ef0358ba91df000e Reviewed-on: https://review.coreboot.org/c/coreboot/+/50847 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> | ||||
| * | util/bucts: Add tool to manipulate BUC.TS bit on Intel targets | Arthur Heymans | 2018-11-19 | 1 | -0/+21 |
| The purpose of this tool is to manipulate and get information about the `Back Up Control, Top Swap` mechanism present on most Intel Southbridges. This tool is initially written by Peter Stuge. This tool makes it possible to have a backup mechanism for the bootblock by using the southbridges Back Up Control Top Swap. Sometimes it is also possible to circumvent vendor write protection mechanisms in order to flash coreboot. An example of where this would be useful would be the Lenovo Thinkpad X60 and T60. Change-Id: I12cc2e91396f096fc979e23848e1929cb6c44fc5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18224 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> | |||||
 |
index : coreboot.git | |
| Coreboot firmware sources | coreboot |
| summaryrefslogtreecommitdiffstats |