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* util/inteltool: Add support for RPL-H CPUMatt DeVillier2024-01-182-0/+7
| | | | | | | | | | | | | | | | | | | | | | Add PCI IDs and descriptor strings to support the integrated north/south bridges and GPU for the i9-13900H CPU. --- CPU: ID 0xb06a2, Processor Type 0x0, Family 0x6, Model 0xba, Stepping 0x2 Northbridge: 8086:a706 (13th generation (Raptor Lake H family) Core Processor) Southbridge: 8086:519d (Raptor Lake) IGD: 8086:a7a0 (Intel(R) Iris Xe Graphics [RPL-P]) SBREG_BAR = 0xfd000000 (MEM) --- TEST=build/run inteltool on Erying SRMJ4 mainboard, verify PCI IDs not unknown, GPIOs dumped. Change-Id: I4cf3f419f103a1a7d4c6850f2257b7e7d45f3b18 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79962 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* inteltool: memory: log PCI id of unknown devicesAlexander Couzens2023-12-041-0/+1
| | | | | | | | Change-Id: I25396e5480c45729710b16345f997c78e8bcbccb Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* inteltool/gpio_names/*.h: Add GPL-2.0-only SPDX license headerNicholas Chin2023-12-0215-0/+30
| | | | | | | | | | | | | Inteltool is GPLv2 licensed so all files that link to it should be GPLv2 by default. In addition, the contents of several of these headers were originally moved directly from gpio_groups.c, which is explicitly marked as GPL-2.0-only. Change-Id: Ie897cb238c0c9e89fe677c999cbf1803f5f4609a Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* util/inteltool: Don't use old style function definitionElyes Haouas2023-08-281-6/+6
| | | | | | | | | | Use "int foo(void)" instead of old-style "int foo()". Change-Id: I609c0332132389c07b03db40dc48dc94ca836a56 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* intetool: Add support for 700 series PCHMichał Żygowski2023-08-096-25/+51
| | | | | | | | | | | | | | The change does the following: - adds PCH IDs for 700 series chipsets per the DOC# 619362 rev 2.2 - updates GPIO table for PCH-S per the DOC# 618659 rev 2.1 - enables dumping GPIOs for 700 series PCH Change-Id: I4509ad714772ce90cdee5135227c02640acb6085 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* util/inteltool: Fix building with musl libcEvgeny Zinoviev2023-06-101-0/+4
| | | | | | | | | | | | 1. Make sure __always_inline is defined. 2. To test if we're on Linux, check presence of __linux__ instead of __GLIBC__. Change-Id: I2ccfc4d2ef4c60877e24508f9926b533cffec0ed Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* util/inteltool: suggest booting with iomem=relaxedPeter Lemenkov2023-06-101-0/+1
| | | | | | | | Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Change-Id: Ib80efd7d1ba516cb0ae4bdb86f95877855195ce0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63999 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/inteltool: Add ADL-S device identificationsMaximilian Brune2023-05-115-0/+15
| | | | | | | | | | | | | R680E, Q670E, H610E are the ADL-S IoT variants see also: commit a0bc90e4abfe ("Add missing ADL-S device identification") Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I1dbfa0464bc22f9bcf91d9e9fa9eb79132600175 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* util/inteltool: Add support for Jasper LakeKarol Zmyslowski2023-04-216-0/+682
| | | | | | | | | | | | Tested on: Intel N5105 (Jasperlake Family, Intel Celeron processor) Based on Intel Pentium Silver and Intel Celeron Processor Datasheet, vol. 2 of 2 revision 001 (DOC# 634545) Change-Id: If4134bd03f5544b5845cde998ee526e5ddd5b51d Signed-off-by: Karol Zmyslowski <karol.zmyslowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* util/inteltool: Fix build on musl-libc systemsFabian Groffen2023-03-121-1/+1
| | | | | | | | | | use __linux__ instead of __GLIBC__ guard for Linux-specific includes Signed-off-by: Fabian Groffen <grobian@gentoo.org> Change-Id: Ifbf4552591c0df7811c5b37a9207c0901b6fd68f Reviewed-on: https://review.coreboot.org/c/coreboot/+/73666 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/inteltool: add support for EBG (Emmitsburg) PCHChristian Walter2023-01-245-0/+454
| | | | | | | | | | | | | | | | | | | | EBG (Emmitsburg) PCH is used in Intel SPR-SP chipset. Its datasheet is Intel doc# 606161. Add Intel Emmitsburg PCH GPIO pin definitions. Also common code change is made to support Intel Emmitsburg PCH: a. Instead of 2 PAD registers per GPIO, it has 4 PAD registers. b. The register address space may not be contiguous from one GPIO group to the next GPIO group. Change-Id: Ia0d9179544020b6abb0be1ecd275a9a46356db8a Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* utils/inteltool: Add support to print Key Locker statusPratikkumar Prajapati2023-01-103-12/+70
| | | | | | | | | | | | | | | | | | Add command-line option "-k" to print status. Sample output: $ inteltool -k ============= Dumping INTEL Key Locker status ============= Key Locker supported : YES AESKL instructions enabled : NO =========================================================== Change-Id: Icb1b08619b1dbc535640127f7ab5f6b49d70a6fe Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
* util/inteltool/Makefile: improve cross-compilation supportMaciej Gabryelski2022-12-091-2/+2
| | | | | | | | | | | Use tool from INSTALL variable to create directory instead of mkdir to be compatible with other cross-compilation buildsystems (like Yocto). Signed-off-by: Maciej Gabryelski <maciej.gabryelski@3mdeb.com> Change-Id: I0b0949d07baae1ae1d7b22ac3d0b8913f81d89c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70104 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/inteltool: Add support for Elkhart lakeKacper Stojek2022-11-106-0/+595
| | | | | | | | | | | Document: 614109, 601458 Tested on: Protectli vault_ehl (VP2420) Signed-off-by: Kacper Stojek <kacper.stojek@3mdeb.com> Change-Id: I54948741082ca1072642046f64539a4c15ddb578 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* util/inteltool: Add support for (non-ULT) BroadwellAngel Pons2022-10-084-0/+14
| | | | | | | | | | Add support for traditional (non-ULT) Broadwell. Change-Id: Ibe0ed9badd580e28060fe8df14a01352d4c1e11e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* util/inteltool: Add 9 series PCH supportAngel Pons2022-10-087-0/+41
| | | | | | | | | | Add the PCI device IDs for 9 series PCHs. Change-Id: Id216cd071b09c93ee6a4792944c6fad39254aa3b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* util/inteltool: Add support for Alderlake P in inteltoolKacper Stojek2022-10-076-1/+644
| | | | | | | | | | | | TEST=Dump registers on Clevo NS70PU with Intel® Core™ i7-1260P Document number: 626817, 630094, 655258 Change-Id: I2ba4ef7eee33d4dd762a05dd755de5e4d2e566dd Signed-off-by: Kacper Stojek <kacper.stojek@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66825 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/inteltool: Add an additional Device ID for Intel HD 4400 GPUArashk Mahshidfar2022-06-222-0/+3
| | | | | | | | | | Add 0x0A16 as a Device ID for Intel HD 4400 Change-Id: I0129376c0ce005c1bfabaa9dbd8d8dfc6c92e5d3 Signed-off-by: Arashk Mahshidfar <arashkmahshidfar@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* inteltool/gpio_names/tigerlake.h: Fix HVMOS pad countMichał Żygowski2022-06-031-1/+1
| | | | | | | | | Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I344fd2db9d53ad5e82240aaa2b766ac0d8a2045d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64464 Reviewed-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* util/inteltool: Add support for Alder Lake chips detection and GPIOsMichał Kopeć2022-05-286-0/+807
| | | | | | | | | | | | | | Add PCI IDs for Alder Lake H devices and their GPIO tables. PCI IDs as per Intel PCH-H EDS Vol1 (doc #619362). TEST=dump GPIOs on i5-12600K with Z690 chipset Change-Id: I0001395517e1e7977b0f808d5d74cf85c52298d6 Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* util/inteltool: Add support for Gemini LakeSean Rhodes2022-05-166-0/+324
| | | | | | | | | | | | Tested on: * StarLite Mk III (N5000) * StarLite Mk IV (N5030) Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I0ef7619c04db66ea0c6e179bdf0a58ed1ab61a48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58537 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* util/inteltool: Add support for Tiger Lake chips detection and GPIOsMichał Żygowski2022-02-156-0/+1503
| | | | | | | | | | | | | Add PCI IDs for Tiger Lake LP and Tiger Lake H devices and their GPIO tables. TEST: dump GPIOs on i5-1135G7, Tiger Lake H untested Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I6071a999be9e8a372997db0369218f297e579d08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* util/inteltool: Actually read SATA init data from SIRDBenjamin Doron2022-02-121-6/+8
| | | | | | | | | | | | | | | | Fix issue where registers always seem to contain their own offset. After writing the desired register into SIRI, the requested data is returned in SIRD. This register is 4 bytes after SIRI, commonly 0xA4. Tested on TGL-H (SATA SIR registers are common), genuine data is returned. Change-Id: I322b11d53178e5b64e353c1b4e576548592c16c3 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* util/inteltool/gpio.c: Correct register nameAngel Pons2021-11-191-2/+2
| | | | | | | | | | | | | Document 319973-003 (ICH10 datasheet) and document 324645-006 (6-series PCH datasheet) indicate that the name of this register is `GP_LVL3`, not `GPIO_LVL3`. Correct the name. Change-Id: I44cc41843c9f7cd0796bd198fb89447d787f155a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* util/inteltool: Add ICH10D PCI IDAngel Pons2021-11-196-1/+8
| | | | | | | | | | | | Add the PCI device ID for the ICH10D southbridge. While we're at it, also fix up whitespace in inteltool.h of an adjacent definition. Change-Id: I98d88a9ce27d3ddaafd7123ee51b2111a8bef019 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* util/inteltool: Add PCH IDs for 200 series chipsetsTimofey Komarov2021-10-245-0/+41
| | | | | | | | Signed-off-by: Timofey Komarov <happycorsair@yandex.ru> Change-Id: Iadad5e79aef9da3fac627adc135525a5001a72b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* inteltool: Support dumping IOBP register valuesIru Cai2021-09-064-1/+324
| | | | | | | | | | | | This patch also adds LynxPoint and WildcatPoint-LP IOBP registers, which is used to get the USB and SATA configuration values for autoport. Change-Id: I1f11640fdff59a5317f19057476f7e48c2956ab9 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41473 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* inteltool: Allow to set cores range for MSRs dumpMaxim Polyakov2021-08-173-5/+38
| | | | | | | | | | | | | | | | | | | | | | Adds the ability to output MSRs dump for the specified range of CPU cores. This makes it easier to reverse engineer server multicore processors using the inteltool utility. The range is set using --cpu-range <start>[-<end>] command line option: $ sudo ./inteltool -M --cpu-range 0-7 $ sudo ./inteltool -M --cpu-range 7-15 $ sudo ./inteltool -M --cpu-range 32 $ sudo ./inteltool -M will print a register dump for all cores, just as before. Change-Id: I3a037cf7ac270d2b51d6e453334c358ff47b4105 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35919 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* inteltool: add initial support for Emmits Burg PCHJonathan Zhang2021-05-102-0/+3
| | | | | | | | | Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: I6a4027bf51b3a189e64211e77621b3dd6c80b00d Reviewed-on: https://review.coreboot.org/c/coreboot/+/52864 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* inteltool: add initial suppot for Sapphire Rapids Scalable ProcessorJonathan Zhang2021-05-102-0/+3
| | | | | | | | | | | Intel Sapphire Rapids Scalable Processor is a 4th generation processor of Intel Xeon Scalable Processor family. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Idf492d6e7993b9d55d6cd865e721c81876cee9a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52863 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* inteltool: Add support to print TME/MKTME statusPratik Prajapati2020-11-303-2/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | Print whether the SOC supports TME/MKTME. If the SOC supports the feature, print the status of enable and lock bit from TME_ACTIVATE MSR. -t option prints this status. Sample output: If TME/MKTME is supported: ============= Dumping INTEL TME/MKTME status ============= TME supported : YES TME locked : YES TME enabled : YES ==================================================== If TME/MKTME is not supported: ============= Dumping INTEL TME status ============= TME supported : NO ==================================================== Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Change-Id: I584ac4b045ba80998d454283e02d3f28ef45692d Reviewed-on: https://review.coreboot.org/c/coreboot/+/45088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* util/inteltool: drop OS-specific rdmsr/wrmsr prototypesIdwer Vollering2020-11-261-2/+0
| | | | | | | | | | | | | | The previous commit (that was not touching inteltool.h) marking internal functions as static is commit 6faccd1f00 Tested on: FreeBSD 13.0-CURRENT r355582 Change-Id: I4aba72f39b528fd70451a4656fd6c835ff766e49 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* util/inteltool/ivy_memory.c: Do not rely on MR0 valuesAngel Pons2020-11-221-15/+24
| | | | | | | | | | | | MR0 may not always be programmed in the training result registers. Thus, do not rely on its values. Also account for per-channel differences. Change-Id: Iaf3b545ea55735b46caf1bd62d5859f2b3efa159 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* util/inteltool/ivy_memory.c: Properly mask tAONPDAngel Pons2020-11-221-1/+1
| | | | | | | | | | | This field is only 4 bits wide. Change-Id: I2cb746e98176d58fc5be423e18babdaa8801b096 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* util/inteltool: add missing special function pads for CNL-LPMichael Niewöhner2020-11-111-0/+166
| | | | | | | | | | | | | | | Add the missing special function gpio pad groups for CNL-LP. The groups and names are documented in the PCH EDS, in Linux (linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places. Also, see soc/intel/tigerlake for reference. Change-Id: I0509552da6ffad395c2b89df1676e1903c783695 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* util/inteltool: add missing special function pads for CNL-HMichael Niewöhner2020-11-111-0/+46
| | | | | | | | | | | | | | | Add the missing special function gpio pad groups for CNL-H. The groups and names are documented in the PCH EDS, in Linux (linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places. Also, see soc/intel/tigerlake for reference. Change-Id: Ib83aeef9f4b6aa174e61ccbd87fb7b6450ed773b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* util/inteltool: add missing native functions of special pads for CNL-HMichael Niewöhner2020-11-111-68/+68
| | | | | | | | | | | | | Add the missing native functions for special gpio pads for CNL-H, which are documented in the PCH EDS and other places. Also, see soc/intel/tigerlake for reference. Change-Id: I71339d66362d29806c91375c214e9fb84c989201 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* util/inteltool: rename GPIO_RSVD_* to their correct names for CNL-HMichael Niewöhner2020-11-111-75/+75
| | | | | | | | | | | | | The names of the GPIO_RSVD_* are documented in the PCH EDS, in Linux (linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places. Also, see soc/intel/tigerlake for reference. Change-Id: Ifd6cabb646000c8dff695c5c4f7196b2779f1430 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* util/inteltool: add missing native functions of special pads for CNL-LPMichael Niewöhner2020-11-111-26/+26
| | | | | | | | | | | | | Add the missing native functions for special gpio pads for CNL-LP, which are documented in the PCH EDS and other places. Also, see soc/intel/tigerlake for reference. Change-Id: Iedb726aa3afdbbbedafb67f6b7668bf591c2b9b4 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* util/inteltool: rename GPIO_RSVD_* to their correct names for CNL-LPMichael Niewöhner2020-11-111-76/+76
| | | | | | | | | | | | | The names of the GPIO_RSVD_* are documented in the PCH EDS, in Linux (linux/drivers/pinctrl/intel/pinctrl-cannonlake.c) and other places. Also, see soc/intel/tigerlake for reference. Change-Id: I86c7159d9f48560c41efdfe49f162aef00499d13 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* util/inteltool: Add support for Intel Lewisburg SKU C621AJingle Hsu2020-11-092-0/+2
| | | | | | | | | | | | Add support for dumping GPIOs on Intel Lewisburg SKU C621A. Tested=On OCP Delta Lake DVT, verify it executes successfully. Change-Id: I58797914aa5816aedace094c179e832150ad5e2e Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47163 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* .gitignore: Ignore .test/.dependencies globallyPatrick Georgi2020-10-311-2/+0
| | | | | | | | | | | These were originally ignored only inside util/ but these files shouldn't be tracked anywhere. Change-Id: Ie0846bd8bdd6e52f420f9dd2e72a8a922102ff90 Signed-off-by: Patrick Georgi <patrick@georgi.software> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* .gitignore: Split into subdirectory filesPatrick Georgi2020-10-301-0/+3
| | | | | | | | | | | | | | There's no need for the global list of files to ignore, so use git's ability to work with more local configuration. Change-Id: I50882e6756cbc0fdfd899353cc23962544690fb3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46879 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* inteltool: Only use real graphics devicesStefan Reinauer2020-10-261-4/+4
| | | | | | | | | | | | | Right now IGD is hard coded to 0:2.0 and if that device is there, it is blindly used, even if it is not a graphics device. Look at the PCI class to make sure we're not using the wrong device. Change-Id: Ia7f52071bd202e2960faba0f46e4fa5e14ad65f8 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* inteltool: initial Hewitt Lake supportStefan Reinauer2020-10-262-0/+3
| | | | | | | | Change-Id: Ifed43d058c70f75d88e9f4b2b07527782ebcbac5 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* util/inteltool: Add support for Comet Lake-UMatt DeVillier2020-08-296-0/+27
| | | | | | | | | | | | | | Add support for 10th-gen/Comet Lake-U based boards: - add PCI IDs for host bridge, IGD, LPC devices - add support for dumping GPIOs, PCRs, etc Tested on an unbranded CML-U board running AMI firmware Change-Id: I44871917565fc628fd1073a6e5c36b6a3246a61c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
* util/inteltool/gpio_names: Make group and community titles consistentBenjamin Doron2020-07-262-5/+5
| | | | | | | | | | | | Consistency is good for scripting and automation. The lowercase "group" in Sunrise Point-LP, for example, was breaking pattern matching used in intelp2m. Change-Id: Iffa8a8ac9c17c5cbd8d7b838d9c703cae6a858b5 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43068 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* inteltool/gpio: Add support for new Lewisburg chipsetsMaxim Polyakov2020-07-213-0/+18
| | | | | | | | | | | | | | | - Add SKUs and Super SKUs of new Lewisburg series chipsets: C621A, C627A, C629A [1]. - These changes allow the utility to generate the GPIO config registers dump. [1] https://review.coreboot.org/c/coreboot/+/40395 Change-Id: I9b63c0a3860a901e58af0c0d5184361661bab5e3 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43534 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/inteltool: add missing L0 and L1 pads for LewisburgMaxim Polyakov2020-07-211-0/+7
| | | | | | | | | | | | | | | The description for L0 and L1 was missed in the datasheet, however, configuration registers for these pads are present. In addition, the chipset contains the "GPP_L0/CSME_INTR_IN" and "GPP_L1/CSME_INTR_OUT" pads in a circuit diagram. Use all available information to add a description for the missed pads. Change-Id: I7a0488c26b3df9de1adc037d94ae290837d65dd8 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40044 Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/inteltool: add PCI ID for ICH10DOIdwer Vollering2020-07-096-0/+7
| | | | | | | | Change-Id: I3561679ef50f4c094d2503539074c957f759ecef Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43321 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-27 22:19:32 +0000