summaryrefslogtreecommitdiffstats
path: root/util
Commit message (Collapse)AuthorAgeFilesLines
* util/lint/kconfig_lint: Fix off by one error that missed last lineMartin Roth2021-11-091-1/+1
| | | | | | | | | | | | | | This error prevented the last line of the Kconfig tree from being printed or added to the output file. This is a significant problem if you try to use the generated file as the kconfig source, because it changes CONFIG_HAVE_RAMSTAGE from defaulting to yes to defaulting to NO. This causes the build to stop working. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: I3ec11f1ac59533a078fd3bd4d0dbee9df825a97a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* amdfwtool: Change the flag value to type boolZheng Bao2021-11-053-33/+33
| | | | | | | | Change-Id: I8bb87e6b16b323b26dd5b411e0063e2e9e333d05 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* amdfwtool: Fix the parameter point to NULL instead of integerZheng Bao2021-11-051-4/+4
| | | | | | | | Change-Id: Iaeeec7a7e2de7847bfcefa5b7ff3f259f86533d4 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* amdfwtool: Change the definition of level to a bitwise formZheng Bao2021-11-051-4/+4
| | | | | | | | Change-Id: Icca393f0d69519cc1c3cb852a11dd7006cf72061 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* util/testing: add code coverage to jenkinsPaul Fagerburg2021-11-041-2/+3
| | | | | | | | | | | | Add COV=1 and the `coverage-report` target to unit test build rules in `what-jenkins-does` so that we get code coverage data from the coreboot and libpayload unit tests. Signed-off-by: Paul Fagerburg <pfagerburg@google.com> Change-Id: I96669c47d1a48e9ab678a4b9cb1d0c8032d727f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* util/spd_tools: Add LP5 support for ADLReka Norman2021-11-044-6/+726
| | | | | | | | | | | | | | | | | | | | | Add LP5 support to spd_tools. Currently, only Intel Alder Lake (ADL) is supported. The SPDs are generated based on a combination of: - The LPDDR5 spec JESD209-5B. - The SPD spec SPD4.1.2.M-2 (the LPDDR3/4 spec is used since JEDEC has not released an SPD spec for LPDDR5). - Intel recommendations in advisory #616599. BUG=b:201234943, b:198704251 TEST=Generate the SPD and manifests for a test part, and check that the SPD matches Intel's expectation. More details in CB:58680. Change-Id: Ic1e68d44f7c0ad64aa9904b7e1297d24bd5db56e Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* SMBIOS/SCONFIG: Allow devtree-defined Type 41 entriesAngel Pons2021-11-047-388/+443
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce the `smbios_dev_info` devicetree keyword to specify the instance ID and RefDes (Reference Designation) of onboard devices. Example syntax: device pci 1c.0 on # PCIe Port #1 device pci 00.0 on smbios_dev_info 6 end end device pci 1c.1 on # PCIe Port #2 device pci 00.0 on smbios_dev_info 42 "PCIe-PCI Time Machine" end end The `SMBIOS_TYPE41_PROVIDED_BY_DEVTREE` Kconfig option enables using this syntax to control the generated Type 41 entries. When this option is enabled, Type 41 entries are only autogenerated for devices with a defined instance ID. This avoids having to keep track of which instance IDs have been used for every device class. Using `smbios_dev_info` when `SMBIOS_TYPE41_PROVIDED_BY_DEVTREE` is not enabled will result in a build-time error, as the syntax is meaningless in this case. This is done with preprocessor guards around the Type 41 members in `struct device` and the code which uses the guarded members. Although the preprocessor usage isn't particularly elegant, adjusting the devicetree syntax and/or grammar depending on a Kconfig option is probably even worse. Change-Id: Iecca9ada6ee1000674cb5dd7afd5c309d8e1a64b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* util/crossgcc/Makefile: Clean up .PHONY definitionsPatrick Georgi2021-11-021-4/+5
| | | | | | | | | | | | | | | | | | | Order functionally: * first "all" and build-$tools * followed by clean * followed by the architecture targets The order was chosen this way because the architecture targets are the mostly likely to continue to grow. While at it, also fix the build_nasm mention (it was build-nasm) and add build_make. Change-Id: Id58338a512d44111b41503d4c14c08be50d51cde Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58796 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/kconfig: Uprev to Linux 5.15's kconfigPatrick Georgi2021-11-021-0/+15
| | | | | | | | | | | Upstream's changes only affect a script that we don't use. Still, this keeps us in sync with the official version. Change-Id: I39cbbfb8dc816b4f36f92e6bd53f40c733691242 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* util/kconfig: Uprev to Linux 5.14's kconfigPatrick Georgi2021-11-022-40/+42
| | | | | | | | | | | | Upstream's changes have been minimal, to the perl script that we don't use and a constness change, so I expect no harm. Still, this keeps us in sync with the official version. Change-Id: I5e5a2400bc3323938da4b946930e2ec119819672 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* util/kconfig: Rewrite patch in quilt's normal formPatrick Georgi2021-11-021-8/+5
| | | | | | | | | | | This is what quilt writes on `quilt refresh` and what it can apply and unapply cleanly. Change-Id: I8c8586da384b65fd5c21c1c1a093642534f83283 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57878 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* buildgcc: Remove GDB from crossgccPatrick Georgi2021-11-0110-161/+18
| | | | | | | | | | | It was added for a specific defunct project by a specific defunct company. Change-Id: Ib56ae0fdc1a50d24ff44c7879c43f8e94a5bfa95 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* amdfwtool: Add PSP ID for combo and ISH header for A/B recoveryZheng Bao2021-10-293-15/+42
| | | | | | | | | | | | | Nobody calls the function until combo or A/B is added, so suppress the warning for now. Test=Majolica (Cezanne) Change-Id: I3082b850fb3fd2d7ae83a1c4dfd89eb7e1bd0f97 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* elogtool: add pytest for elogtoolRicardo Quesada2021-10-253-0/+188
| | | | | | | | | | | | | | | | This CL adds a python test for elogtool. It tests the basic functionality of elogtool: list, clear and add. A future CL will include more complex tests. BUG=b:172210863 TEST=pytest elogtool_test.py Change-Id: If1241ad070d1c690c84f5ca61c0487ba27c2a287 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* util/inteltool: Add PCH IDs for 200 series chipsetsTimofey Komarov2021-10-245-0/+41
| | | | | | | | Signed-off-by: Timofey Komarov <happycorsair@yandex.ru> Change-Id: Iadad5e79aef9da3fac627adc135525a5001a72b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55839 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* util/release/build-release: Create cross-toolchain version fileFelix Singer2021-10-211-0/+2
| | | | | | | | | | | Add cross-toolchain version file to the release tarball, which can be used for pre-setting the variables used in buildgcc. Change-Id: Iad1e0adaa95b71f161caf978276bfb0a63eac8f4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58399 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* util/crossgcc/buildgcc: Use pre-set CROSSGCC_VERSION if possibleFelix Singer2021-10-211-1/+3
| | | | | | | | | | | | | | | | For reproducibility, a version string is appended to the version of the tools used in the cross-toolchain. Currently, git is used to determine that version string at runtime of this script. There are cases, where it's not possible to determine that version string, e.g. when a release tarball is used, and if so, the version string is just `v_`. Thus, allow pre-setting the variable `CROSSGCC_VERSION`. Change-Id: I888ccd877c93436b5e033528c43bd8667b8d2f10 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* util/crossgcc/buildgcc: Allow printing only the versionFelix Singer2021-10-201-2/+4
| | | | | | | | | | | | | In preperation to CB:58396, add the parameter `-W|--print-version`, which allows printing the content of `CROSSGCC_VERSION`. In combination with CB:58396, this can be used to pre-set the variable in case of the git history is not accessible. Change-Id: I9a205ca0ecb0ece47eb5d8fa73706478354512ff Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* util/crossgcc/buildgcc: Remove CROSSGCC_COMMITFelix Singer2021-10-201-2/+1
| | | | | | | | | | | | | | For reproducibility, the buildgcc script is copied to the destination folder of the toolchain. `CROSSGCC_COMMIT` is used as a file name extension for the script and was introduced when `CROSSGCC_VERSION` didn't contain the commit yet. Since this is not the case anymore, remove it. Change-Id: Id0a0b657eb828b2728ff787228eaa38be83d9517 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58450 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/cbfstool/rmodule: Omit undefined extern symbols from reloc tableRaul E Rangel2021-10-201-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When using `DECLARE_OPTIONAL_REGION`, it is assumed that REGION_SIZE(name) == 0 if the region was not defined in the memlayout. When using non-rmodule stages (i.e., bootblock, romstage, etc), this assumption holds true, but breaks down in rmodule (i.e., ramstage) stages. The rmodule tool is not currently omitting undefined externals from the relocation table. e.g., extern u8 _##name##_size[]; This means that when the rmodule loader runs, it will rewrite the symbol from 0 (which is the default the linker assumed) to 0 + offset. This is wrong since the symbol doesn't actually exist. Instead we need to omit the relocation so it continues to keep the default value of 0. BUG=b:179699789 TEST=Print out REGION_SIZE(cbfs_cache) in ramstage and verify it is set to 0. I also see the following printed by the rmodtool now: DEBUG: Omitting relocation for undefined extern: _watchdog_tombstone_size DEBUG: Omitting relocation for undefined extern: _watchdog_tombstone DEBUG: Omitting relocation for undefined extern: _watchdog_tombstone DEBUG: Omitting relocation for absolute symbol: _stack_size DEBUG: Omitting relocation for absolute symbol: _program_size DEBUG: Omitting relocation for absolute symbol: _cbmem_init_hooks_size DEBUG: Omitting relocation for absolute symbol: _payload_preload_cache_size DEBUG: Omitting relocation for absolute symbol: _payload_preload_cache DEBUG: Omitting relocation for absolute symbol: _payload_preload_cache_size DEBUG: Omitting relocation for absolute symbol: _payload_preload_cache DEBUG: Omitting relocation for undefined extern: _cbfs_cache DEBUG: Omitting relocation for undefined extern: _cbfs_cache_size As you can see the _watchdog_tombstone will also be fixed by this CL. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib57e263fa9014da4f6854637000c1c8ad8eb351a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* kconfig_lint: use just one variable for keeping track of choicesMichael Niewöhner2021-10-201-10/+3
| | | | | | | | | | | | Instead of using two variables, one for the boolean value and one for the path, use just one with the path. Since an empty string evalutes to false, this simplification does not change behaviour. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I2f1171789af6815094446f107f3c634332a3427e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* kconfig_lint: put $inside_choice together right in the first placeMichael Niewöhner2021-10-201-2/+2
| | | | | | | | | | | Instead of substituting the delimiter later, put $inside_choice together right in the first place. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Ia713510a683101c48c86a1c3722ebb1607a29288 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
* util/cse_serger: Add command `create-cse-region`Furquan Shaikh2021-10-191-0/+100
| | | | | | | | | | | | | | This change adds a new command `create-cse-region` to cse_serger tool which takes as inputs offset:size and file for different CSE partitions and generates the entire CSE region image. BUG=b:189177186 Change-Id: Ib087f5516e5beb6390831ef4e34b0b067d3fbc8b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58215 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* util/cse_serger: Replace cse_layout_regions with array of regionsFurquan Shaikh2021-10-194-38/+49
| | | | | | | | | | | | | | This change replaces `struct cse_layout_regions` with an array of `struct region` and introduces enums for DP and BP[1-4]. This makes it easier to loop over the different regions in following changes. BUG=b:189177186 Change-Id: If3cced4506d26dc534047cb9c385aaa9418d8522 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* util/cse*: Add cse_helpers.{c,h}Furquan Shaikh2021-10-197-84/+76
| | | | | | | | | | | | | | This change moves `read_member` and `write_member` helper functions out of cse_fpt.c and cse_serger.c into cse_helpers.c to avoid duplication. BUG=b:189177186,b:189167923 Change-Id: I7b646b29c9058d892bb0fc9824ef1b4340d2510c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* util/cse_serger: Add a new tool for stitching CSE componentsFurquan Shaikh2021-10-1910-2/+1957
| | | | | | | | | | | | | This change adds a new tool `cse_serger` which can be used to print, dump and stitch together different components for the CSE region. BUG=b:189177186 Change-Id: I90dd809b47fd16afdc80e66431312721082496aa Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* util/cse_fpt: Add a new tool for managing Intel CSE FPT binariesFurquan Shaikh2021-10-197-2/+715
| | | | | | | | | | | | | This change adds a new tool `cse_fpt` which can be used to print and dump CSE partitions in Flash Partition Table (FPT) format. BUG=b:189167923 Change-Id: I93c8d33e9baa327cbdab918a14f2f7a039953be6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* util/amdfwtool: rename PSP related embedded_firmware struct elementsFelix Held2021-10-192-5/+5
| | | | | | | | | | | | | | | The element at offset 0x14 in the embedded_firmware struct is the pointer to the combo PSP directory header, so rename it from comboable to combo_psp_directory to clarify that this is not a flag, but a pointer to a data structure. Also rename psp_entry to psp_directory since it points to the PSP directory table. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic6149c17ae813f4dcea71c308054849a1a2e4394 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* cbfstool: Add helper function `buffer_from_file_aligned_size`Furquan Shaikh2021-10-182-3/+18
| | | | | | | | | | | | | | | This change adds a helper function `buffer_from_file_aligned_size` that loads a file into memory buffer by creating a memory buffer of size rounded up to the provided `size_granularity` parameter. BUG=b:189177186,b:189167923 Change-Id: Iad3430d476abcdad850505ac50e36cd5d5deecb4 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* kconfig_lint: Drop overly restrictive rule about choice configsNico Huber2021-10-181-10/+1
| | | | | | | | | | | | | | | | | | | | This rule was creating trouble: * A symbol may only be declared inside or outside a choice. The linter treats every occurence of a `config` entry as a symbol declaration, even when it's just setting a default or adding selects. This is not easy to fix as the symbol objects are not created first and then added to the $symbols array when we know what kind of decla- ration we have, but are created incrementally inside this global list. Change-Id: I48a17f6403470251be6b6d44bb82a8bdcbefe9f6 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56410 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* libpayload: Add unit-tests framework and first test caseJakub Czapiga2021-10-181-0/+1
| | | | | | | | | | | | | This commit adds a unit-tests framework ported from coreboot, and test for drivers/speaker. Usage of the unit-tests framework is same as for the coreboot one. Change-Id: Iaa94ee4dcdc3f74af830113813df0e8fb0b31e4f Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mainboard: Drop invalid `VGA_BIOS_FILE` defaultsAngel Pons2021-10-151-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | If the VGA BIOS file path for `VGA_BIOS_FILE` in a mainboard's Kconfig does not exist in the coreboot tree (including submodules), drop it. These files should be stored in the `site-local` subdirectory and the paths specified for each board in `site-local/Kconfig`. For example: config VGA_BIOS_FILE default "site-local/x200_vbios.bin" if BOARD_LENOVO_X200 Note that this is just an example. There are better ways to structure one's `site-local` subfolder. Using the `CONFIG_MAINBOARD_DIR` option would be one of them, though variants may still need special handling. Also, update autoport to not generate `VGA_BIOS_FILE` defaults. Change-Id: I1b5dfba035a42d7943f270f95fb7d32b285584d2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* util/autoport/bd82x6x.go: Fix includesNicholas Chin2021-10-121-1/+2
| | | | | | | | | | | | | | Fix include of nvs.h to reflect commit 661ad4666c (ACPI: Select ACPI_SOC_NVS only where suitable); and re-add <device/pci_ops.h>, removed in commit 0aad0531dc (util/autoport/bd82x6x.go: Drop unused includes), as the generated early_init.c uses pci_write_config16(). Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Change-Id: Ic1e97cfa7dce0e4d25f7a37c28d3635bdbf6c2a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* util/cbfstool: Add support for ARM64 UefiPayloadRex-BC Chen2021-10-042-2/+3
| | | | | | | | | | | | | UEFI payload is supported on some ARM64 platforms, for example MT8195. As a result, add MACHINE_TYPE_ARM64 to support ARM SystemReady. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I4c0c6e263bd2f518a62ff9db44d72dd31086756a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* util/liveiso: Install nvme-cli toolFelix Singer2021-10-011-0/+1
| | | | | | | | | | | nvme-cli is used to manage NVMe devices and it supports many vendors. Also, it seems it's commonly used to do firmware updates. Change-Id: I26a78867b01d3af0441827c5b25343a46d7ddea1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* Revert "Revert "util/abuild: Regenerate xcompile on every abuild run""Reka Norman2021-09-261-0/+1
| | | | | | | | | | | | | | | | | | | | This reverts commit d94f8bbe9da290e120df20bf244920436e9510e7. This is a reland of https://review.coreboot.org/57651. The original change broke parallel abuild runs since the xcompile file was deleted by every recursive call to abuild. This issue was fixed by rebasing on top of a change which only regenerates the xcompile on non-recursive calls. BUG=None TEST=Parallel abuild run succeeds. Change-Id: I086ba7b2ae1b8b14459838bd18ce962a84aa306d Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57913 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* elogtool: Fix off-by-one error in month in timestampRicardo Quesada2021-09-241-1/+2
| | | | | | | | | | | | | | | | elogtool was setting the timestamp with the wrong value in the month. This CL fixes that by incrementing the month by one. This is needed since gmtime() returns the month value starting at 0. TEST=pytest elogtool_test.py (see next CL in relation chain) Change-Id: I00f89ed99b049caafba2e47feae3c068245f9021 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* util/abuild: Run `make .xcompile` only onceNico Huber2021-09-241-4/+4
| | | | | | | | | | | | | If abuild called itself recursively, the file already exists and we can spare us one evaluation of all the makefiles per recursive abuild run. Change-Id: Id3e2239354ec251c24c03c971987586deeb026c5 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42640 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* kconfig_lint: restrict definition of defaults for choice elementsMichael Niewöhner2021-09-231-0/+9
| | | | | | | | | | | | | Defining defaults for symbols used inside choices is not allowed. Add a check for this, so we can drop the existent, overly restrictive checks in the follow-up change. Change-Id: I45bce2633dbd168fceb81ceae9b68621b28526e8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Martin Roth <martinroth@google.com>
* util/crossgcc: Update gcc to 11.2Patrick Georgi2021-09-2311-21485/+25
| | | | | | | | | | | Various fixes to gnat and the improved nds32 backend have been merged into gcc by now, so we don't need to carry those patches anymore. Change-Id: Icdee2a8beedd109ee1f0eef6f32f7accbf66674b Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* util/spd_tools: Remove old lp4x and ddr4 versions of spd_toolsReka Norman2021-09-239-4115/+0
| | | | | | | | | | | | | | | The migration to the new unified version of spd_tools is complete, so the old lp4x and ddr4 versions can be removed. BUG=b:191776301 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I6b1fc297739efc8dc7d7eec64956bf3343984604 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* util/spd_tools: Sort platforms_manifest entries by set numberReka Norman2021-09-231-3/+10
| | | | | | | | | | | | | | | Ensure that the order of entries in each platform manifest is consistent every time spd_gen is run. BUG=b:191776301 TEST=Run spd_gen for lp4x and ddr4, check that the manifests are unchanged. Change-Id: I7bfea65c8fc781df80a8725c0cf20c7547c857e8 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* util/mb/google: Update templates to refer to the new spd_toolsReka Norman2021-09-2314-21/+21
| | | | | | | | | | | | | | | | | Update the new variant templates to refer to the new unified version of spd_tools: - Update the comments in mem_parts_used.txt - Change the placeholder SPD in Makefile.inc to 'placeholder' BUG=b:191776301 TEST=None Change-Id: I03265de0d1182da81dd25a2fe6f940a0b82e5fa4 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* amdfwtool: Add an optional column of levelZheng Bao2021-09-231-6/+79
| | | | | | | | | | | | | | | | | | The value of level defined in table is the default one. We now give an extra option in config file to change this value so some FWs can be dropped in a more optimized way. For the non A/B recovery mode, The value could be L1, L2, Lb or Lx, which are level 1, leve 2, level both and using default value. If it is empty or Lx, left the level in table unchanged. Give a redundant field [12bxBX] in regular exprssion for A/B recovery which will be done later. Change-Id: I0847bc3793467a2299f14d1d2d2486f3f858d7f3 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* util/spd_tools: Remove PLK platformReka Norman2021-09-233-4/+1
| | | | | | | | | | | | | | | Currently spd_tools treats PCO and PLK as separate platforms. This is unnecessary since they have the same SPD requirements. Remove PLK, and use PCO as the platform for all zork variants. BUG=b:191776301 TEST=None Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I7eeeab53fb3e0d92c3675fb80b4747297d4257ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/57771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* util/spd_tools: Add README for unified spd_toolsReka Norman2021-09-231-0/+495
| | | | | | | | | | | | | | | | Combine the existing lp4x and ddr4 READMEs into a single file, and update it to reflect the new unified version of the tools. BUG=b:191776301 TEST=None Change-Id: I866932a1d0b5b6b47b0daff893b37de7a302b4e6 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* util/spd_tools: Add 'Generated by' string to part_id_gen output filesReka Norman2021-09-211-6/+10
| | | | | | | | | | | | | | | Add a 'Generated by' string to the generated Makefile.inc and dram_id.generated.txt, showing the command used to generate the files. BUG=b:191776301 TEST=Run part_id_gen, check that the generated files contain the string Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: Ic9a7826212a732288f36f111b7bc20365a1f702d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
* util/spd_tools: Automatically determine the SPD dir in part_id_genReka Norman2021-09-211-20/+117
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, one of the arguments to part_id_gen is the directory containing the SPD files, e.g. spd/lp4x/set-0. This requires the user of the tool to understand the spd/ directory structure, and manually look up the set number corresponding to their platform. Change part_id_gen to take the platform and memory technology as arguments instead of the SPD directory, and automatically determine the SPD directory by reading the platforms manifest file generated by spd_gen.go. BUG=b:191776301 TEST=Run part_id_gen and check that the generated Makefile.inc and dram_id.generated.txt are the same as before. Example: util/spd_tools/bin/part_id_gen \ ADL \ lp4x \ src/mainboard/google/brya/variants/kano/memory \ src/mainboard/google/brya/variants/kano/memory/mem_parts_used.txt Change-Id: I7cd7243d76b5769e8a15daa56b8438274bdd8e96 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* util/spd_tools: Add max ID check for auto-generated IDs to part_id_genReka Norman2021-09-211-0/+3
| | | | | | | | | | | | | | | | Currently, the maximum part ID of 15 is enforced only for manually assigned IDs. Also enforce it for automatically assigned IDs. BUG=b:191776301 TEST=part_id_gen fails when the number of part IDs which would be assigned is greater than MaxMemoryId. Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I802190a13b68439ccbcdb28300ccc5fd1b38a9c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57691 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* util: Add DDR4 generic SPD for 4JQA-0622ADFrank Wu2021-09-211-0/+11
| | | | | | | | | | | | | | | Add SPD support for DDR4 memory part BUG=b:199469240 TEST=none Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Ie67cf6b90304f0bcf80838866c7461c0cea86dc3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-05 04:38:57 +0000